/**
 ******************************************************************************
 * @file           : main.c
 * @author         : Auto-generated by STM32CubeIDE
 * @brief          : Main program body
 ******************************************************************************
 * @attention
 *
 * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
 * All rights reserved.</center></h2>
 *
 * This software component is licensed by ST under BSD 3-Clause license,
 * the "License"; You may not use this file except in compliance with the
 * License. You may obtain a copy of the License at:
 *                        opensource.org/licenses/BSD-3-Clause
 *
 ******************************************************************************
 */

#include "stm32l073xx.h"

#if !defined(__SOFT_FP__) && defined(__ARM_FP)
  #warning "FPU is not initialized, but the project is compiling for an FPU. Please initialize the FPU before use."
#endif

#define VELIKOST_DAT 1000
uint32_t data1[VELIKOST_DAT];

void prenosDat(uint32_t pocetIteraci)
{
	uint32_t data2[VELIKOST_DAT];

	for(uint32_t x = 0U; x < pocetIteraci; x++)
	{
		for(uint32_t y = 0U; y < VELIKOST_DAT; y++)
		{
			data1[y] = (data2[y])++;
		}
	}
}

void nastavHSI(void)
{
	// zapne cekaci stav
	FLASH->ACR |= FLASH_ACR_LATENCY;

	// zapne interni vysokorychlostni oscilator
	RCC->CR |= RCC_CR_HSION;

	// cekej, dokud HSI neni pripraveny
	while (!(RCC->CR & RCC_CR_HSIRDY));

	// nastavi HSI jako zdroj hodinoveho signalu
	RCC->CFGR |= RCC_CFGR_SW_HSI;

	// cekej, dokud neni zdroj prepnuty
	while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI);

	// vypne interni vicerychlostni oscilator
	RCC->CR &= ~RCC_CR_MSION;
}

void zapniPll(void)
{
	// Zapne PLL
	RCC->CR |= RCC_CR_PLLON;

	// cekej, dokud neni PLL pripraven
	while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);

	// nastavi PLL jako zdroj hodinoveho signalu
	RCC->CFGR |= RCC_CFGR_SW_PLL;

	// cekej, dokud neni zdroj prepnuty
	while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);

	// vypne interni vicerychlostni oscilator
	RCC->CR &= ~RCC_CR_MSION;
}

void nastavPll_16(void)
{
	// zapne interni vysokorychlostni oscilator
	RCC->CR |= RCC_CR_HSION;

	// cekej, dokud HSI neni pripraveny
	while (!(RCC->CR & RCC_CR_HSIRDY));

	// zapne cekaci stav
	FLASH->ACR |= FLASH_ACR_LATENCY;

	// PLL nasobi 3x -> 48 MHz
	RCC->CFGR |= RCC_CFGR_PLLMUL3;

	// PLL deli 3x -> 16 MHz
	RCC->CFGR |= RCC_CFGR_PLLDIV3;

	zapniPll();
}

void nastavPll_4(void)
{
	// zapne interni vysokorychlostni oscilator
	RCC->CR |= RCC_CR_HSION;

	// cekej, dokud HSI neni pripraveny
	while (!(RCC->CR & RCC_CR_HSIRDY));

	// vydeli HSI 4x -> 4 MHz
	RCC->CR |= RCC_CR_HSIDIVEN;

	// zapne cekaci stav
	FLASH->ACR |= FLASH_ACR_LATENCY;

	// PLL nasobi 8x -> 32 MHz
	RCC->CFGR |= RCC_CFGR_PLLMUL8;

	// PLL deli 2x -> 16 MHz
	RCC->CFGR |= RCC_CFGR_PLLDIV2;

	zapniPll();
}

void nastavPll_4EXT(void)
{
	// zapne HSE
	RCC->CR |= (RCC_CR_CSSHSEON | RCC_CR_HSEON);

	// cekej, dokud neni HSE pripraven
	while((RCC->CR & RCC_CR_HSERDY) != RCC_CR_HSERDY);

	// zapne cekaci stav
	FLASH->ACR |= FLASH_ACR_LATENCY;

	// PLL nasobi 8x -> 32 MHz
	RCC->CFGR |= RCC_CFGR_PLLMUL8;

	// PLL deli 2x -> 16 MHz
	RCC->CFGR |= RCC_CFGR_PLLDIV2;

	// HSE vstupem PLL
	RCC->CFGR |= RCC_CFGR_PLLSRC;

	zapniPll();
}

void nastavPll_2EXT(void)
{
	// zapne HSE
	RCC->CR |= (RCC_CR_CSSHSEON | RCC_CR_HSEON);

	// cekej, dokud neni HSE pripraven
	while((RCC->CR & RCC_CR_HSERDY) != RCC_CR_HSERDY);

	// zapne cekaci stav
	FLASH->ACR |= FLASH_ACR_LATENCY;

	// PLL nasobi 16x -> 32 MHz
	RCC->CFGR |= RCC_CFGR_PLLMUL16;

	// PLL deli 2x -> 16 MHz
	RCC->CFGR |= RCC_CFGR_PLLDIV2;

	// HSE vstupem PLL
	RCC->CFGR |= RCC_CFGR_PLLSRC;

	zapniPll();
}

int main(void)
{
	nastavHSI();
	//nastavPll_16();
	//nastavPll_4();
	//nastavPll_4EXT();
	//nastavPll_2EXT();

	while(1)
	{
		prenosDat(3000);
	}
}
