
lptimtest.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   000000c0  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         000018ec  080000c0  080000c0  000100c0  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       0000001c  080019ac  080019ac  000119ac  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  080019c8  080019c8  0002000c  2**0
                  CONTENTS
  4 .ARM          00000000  080019c8  080019c8  0002000c  2**0
                  CONTENTS
  5 .preinit_array 00000000  080019c8  080019c8  0002000c  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  080019c8  080019c8  000119c8  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  080019cc  080019cc  000119cc  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         0000000c  20000000  080019d0  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00000050  2000000c  080019dc  0002000c  2**2
                  ALLOC
 10 ._user_heap_stack 00000604  2000005c  080019dc  0002005c  2**0
                  ALLOC
 11 .ARM.attributes 00000028  00000000  00000000  0002000c  2**0
                  CONTENTS, READONLY
 12 .debug_info   00004eb7  00000000  00000000  00020034  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_abbrev 00001145  00000000  00000000  00024eeb  2**0
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_aranges 00000620  00000000  00000000  00026030  2**3
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_ranges 00000578  00000000  00000000  00026650  2**3
                  CONTENTS, READONLY, DEBUGGING
 16 .debug_macro  00012b1b  00000000  00000000  00026bc8  2**0
                  CONTENTS, READONLY, DEBUGGING
 17 .debug_line   0000531a  00000000  00000000  000396e3  2**0
                  CONTENTS, READONLY, DEBUGGING
 18 .debug_str    0007475a  00000000  00000000  0003e9fd  2**0
                  CONTENTS, READONLY, DEBUGGING
 19 .comment      0000007b  00000000  00000000  000b3157  2**0
                  CONTENTS, READONLY
 20 .debug_frame  00001428  00000000  00000000  000b31d4  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

080000c0 <__do_global_dtors_aux>:
 80000c0:	b510      	push	{r4, lr}
 80000c2:	4c06      	ldr	r4, [pc, #24]	; (80000dc <__do_global_dtors_aux+0x1c>)
 80000c4:	7823      	ldrb	r3, [r4, #0]
 80000c6:	2b00      	cmp	r3, #0
 80000c8:	d107      	bne.n	80000da <__do_global_dtors_aux+0x1a>
 80000ca:	4b05      	ldr	r3, [pc, #20]	; (80000e0 <__do_global_dtors_aux+0x20>)
 80000cc:	2b00      	cmp	r3, #0
 80000ce:	d002      	beq.n	80000d6 <__do_global_dtors_aux+0x16>
 80000d0:	4804      	ldr	r0, [pc, #16]	; (80000e4 <__do_global_dtors_aux+0x24>)
 80000d2:	e000      	b.n	80000d6 <__do_global_dtors_aux+0x16>
 80000d4:	bf00      	nop
 80000d6:	2301      	movs	r3, #1
 80000d8:	7023      	strb	r3, [r4, #0]
 80000da:	bd10      	pop	{r4, pc}
 80000dc:	2000000c 	.word	0x2000000c
 80000e0:	00000000 	.word	0x00000000
 80000e4:	08001994 	.word	0x08001994

080000e8 <frame_dummy>:
 80000e8:	4b04      	ldr	r3, [pc, #16]	; (80000fc <frame_dummy+0x14>)
 80000ea:	b510      	push	{r4, lr}
 80000ec:	2b00      	cmp	r3, #0
 80000ee:	d003      	beq.n	80000f8 <frame_dummy+0x10>
 80000f0:	4903      	ldr	r1, [pc, #12]	; (8000100 <frame_dummy+0x18>)
 80000f2:	4804      	ldr	r0, [pc, #16]	; (8000104 <frame_dummy+0x1c>)
 80000f4:	e000      	b.n	80000f8 <frame_dummy+0x10>
 80000f6:	bf00      	nop
 80000f8:	bd10      	pop	{r4, pc}
 80000fa:	46c0      	nop			; (mov r8, r8)
 80000fc:	00000000 	.word	0x00000000
 8000100:	20000010 	.word	0x20000010
 8000104:	08001994 	.word	0x08001994

08000108 <__udivsi3>:
 8000108:	2200      	movs	r2, #0
 800010a:	0843      	lsrs	r3, r0, #1
 800010c:	428b      	cmp	r3, r1
 800010e:	d374      	bcc.n	80001fa <__udivsi3+0xf2>
 8000110:	0903      	lsrs	r3, r0, #4
 8000112:	428b      	cmp	r3, r1
 8000114:	d35f      	bcc.n	80001d6 <__udivsi3+0xce>
 8000116:	0a03      	lsrs	r3, r0, #8
 8000118:	428b      	cmp	r3, r1
 800011a:	d344      	bcc.n	80001a6 <__udivsi3+0x9e>
 800011c:	0b03      	lsrs	r3, r0, #12
 800011e:	428b      	cmp	r3, r1
 8000120:	d328      	bcc.n	8000174 <__udivsi3+0x6c>
 8000122:	0c03      	lsrs	r3, r0, #16
 8000124:	428b      	cmp	r3, r1
 8000126:	d30d      	bcc.n	8000144 <__udivsi3+0x3c>
 8000128:	22ff      	movs	r2, #255	; 0xff
 800012a:	0209      	lsls	r1, r1, #8
 800012c:	ba12      	rev	r2, r2
 800012e:	0c03      	lsrs	r3, r0, #16
 8000130:	428b      	cmp	r3, r1
 8000132:	d302      	bcc.n	800013a <__udivsi3+0x32>
 8000134:	1212      	asrs	r2, r2, #8
 8000136:	0209      	lsls	r1, r1, #8
 8000138:	d065      	beq.n	8000206 <__udivsi3+0xfe>
 800013a:	0b03      	lsrs	r3, r0, #12
 800013c:	428b      	cmp	r3, r1
 800013e:	d319      	bcc.n	8000174 <__udivsi3+0x6c>
 8000140:	e000      	b.n	8000144 <__udivsi3+0x3c>
 8000142:	0a09      	lsrs	r1, r1, #8
 8000144:	0bc3      	lsrs	r3, r0, #15
 8000146:	428b      	cmp	r3, r1
 8000148:	d301      	bcc.n	800014e <__udivsi3+0x46>
 800014a:	03cb      	lsls	r3, r1, #15
 800014c:	1ac0      	subs	r0, r0, r3
 800014e:	4152      	adcs	r2, r2
 8000150:	0b83      	lsrs	r3, r0, #14
 8000152:	428b      	cmp	r3, r1
 8000154:	d301      	bcc.n	800015a <__udivsi3+0x52>
 8000156:	038b      	lsls	r3, r1, #14
 8000158:	1ac0      	subs	r0, r0, r3
 800015a:	4152      	adcs	r2, r2
 800015c:	0b43      	lsrs	r3, r0, #13
 800015e:	428b      	cmp	r3, r1
 8000160:	d301      	bcc.n	8000166 <__udivsi3+0x5e>
 8000162:	034b      	lsls	r3, r1, #13
 8000164:	1ac0      	subs	r0, r0, r3
 8000166:	4152      	adcs	r2, r2
 8000168:	0b03      	lsrs	r3, r0, #12
 800016a:	428b      	cmp	r3, r1
 800016c:	d301      	bcc.n	8000172 <__udivsi3+0x6a>
 800016e:	030b      	lsls	r3, r1, #12
 8000170:	1ac0      	subs	r0, r0, r3
 8000172:	4152      	adcs	r2, r2
 8000174:	0ac3      	lsrs	r3, r0, #11
 8000176:	428b      	cmp	r3, r1
 8000178:	d301      	bcc.n	800017e <__udivsi3+0x76>
 800017a:	02cb      	lsls	r3, r1, #11
 800017c:	1ac0      	subs	r0, r0, r3
 800017e:	4152      	adcs	r2, r2
 8000180:	0a83      	lsrs	r3, r0, #10
 8000182:	428b      	cmp	r3, r1
 8000184:	d301      	bcc.n	800018a <__udivsi3+0x82>
 8000186:	028b      	lsls	r3, r1, #10
 8000188:	1ac0      	subs	r0, r0, r3
 800018a:	4152      	adcs	r2, r2
 800018c:	0a43      	lsrs	r3, r0, #9
 800018e:	428b      	cmp	r3, r1
 8000190:	d301      	bcc.n	8000196 <__udivsi3+0x8e>
 8000192:	024b      	lsls	r3, r1, #9
 8000194:	1ac0      	subs	r0, r0, r3
 8000196:	4152      	adcs	r2, r2
 8000198:	0a03      	lsrs	r3, r0, #8
 800019a:	428b      	cmp	r3, r1
 800019c:	d301      	bcc.n	80001a2 <__udivsi3+0x9a>
 800019e:	020b      	lsls	r3, r1, #8
 80001a0:	1ac0      	subs	r0, r0, r3
 80001a2:	4152      	adcs	r2, r2
 80001a4:	d2cd      	bcs.n	8000142 <__udivsi3+0x3a>
 80001a6:	09c3      	lsrs	r3, r0, #7
 80001a8:	428b      	cmp	r3, r1
 80001aa:	d301      	bcc.n	80001b0 <__udivsi3+0xa8>
 80001ac:	01cb      	lsls	r3, r1, #7
 80001ae:	1ac0      	subs	r0, r0, r3
 80001b0:	4152      	adcs	r2, r2
 80001b2:	0983      	lsrs	r3, r0, #6
 80001b4:	428b      	cmp	r3, r1
 80001b6:	d301      	bcc.n	80001bc <__udivsi3+0xb4>
 80001b8:	018b      	lsls	r3, r1, #6
 80001ba:	1ac0      	subs	r0, r0, r3
 80001bc:	4152      	adcs	r2, r2
 80001be:	0943      	lsrs	r3, r0, #5
 80001c0:	428b      	cmp	r3, r1
 80001c2:	d301      	bcc.n	80001c8 <__udivsi3+0xc0>
 80001c4:	014b      	lsls	r3, r1, #5
 80001c6:	1ac0      	subs	r0, r0, r3
 80001c8:	4152      	adcs	r2, r2
 80001ca:	0903      	lsrs	r3, r0, #4
 80001cc:	428b      	cmp	r3, r1
 80001ce:	d301      	bcc.n	80001d4 <__udivsi3+0xcc>
 80001d0:	010b      	lsls	r3, r1, #4
 80001d2:	1ac0      	subs	r0, r0, r3
 80001d4:	4152      	adcs	r2, r2
 80001d6:	08c3      	lsrs	r3, r0, #3
 80001d8:	428b      	cmp	r3, r1
 80001da:	d301      	bcc.n	80001e0 <__udivsi3+0xd8>
 80001dc:	00cb      	lsls	r3, r1, #3
 80001de:	1ac0      	subs	r0, r0, r3
 80001e0:	4152      	adcs	r2, r2
 80001e2:	0883      	lsrs	r3, r0, #2
 80001e4:	428b      	cmp	r3, r1
 80001e6:	d301      	bcc.n	80001ec <__udivsi3+0xe4>
 80001e8:	008b      	lsls	r3, r1, #2
 80001ea:	1ac0      	subs	r0, r0, r3
 80001ec:	4152      	adcs	r2, r2
 80001ee:	0843      	lsrs	r3, r0, #1
 80001f0:	428b      	cmp	r3, r1
 80001f2:	d301      	bcc.n	80001f8 <__udivsi3+0xf0>
 80001f4:	004b      	lsls	r3, r1, #1
 80001f6:	1ac0      	subs	r0, r0, r3
 80001f8:	4152      	adcs	r2, r2
 80001fa:	1a41      	subs	r1, r0, r1
 80001fc:	d200      	bcs.n	8000200 <__udivsi3+0xf8>
 80001fe:	4601      	mov	r1, r0
 8000200:	4152      	adcs	r2, r2
 8000202:	4610      	mov	r0, r2
 8000204:	4770      	bx	lr
 8000206:	e7ff      	b.n	8000208 <__udivsi3+0x100>
 8000208:	b501      	push	{r0, lr}
 800020a:	2000      	movs	r0, #0
 800020c:	f000 f806 	bl	800021c <__aeabi_idiv0>
 8000210:	bd02      	pop	{r1, pc}
 8000212:	46c0      	nop			; (mov r8, r8)

08000214 <__aeabi_uidivmod>:
 8000214:	2900      	cmp	r1, #0
 8000216:	d0f7      	beq.n	8000208 <__udivsi3+0x100>
 8000218:	e776      	b.n	8000108 <__udivsi3>
 800021a:	4770      	bx	lr

0800021c <__aeabi_idiv0>:
 800021c:	4770      	bx	lr
 800021e:	46c0      	nop			; (mov r8, r8)

08000220 <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 8000220:	b580      	push	{r7, lr}
 8000222:	af00      	add	r7, sp, #0
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 8000224:	f000 f992 	bl	800054c <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 8000228:	f000 f810 	bl	800024c <SystemClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 800022c:	f000 f8b0 	bl	8000390 <MX_GPIO_Init>
  MX_LPTIM1_Init();
 8000230:	f000 f886 	bl	8000340 <MX_LPTIM1_Init>

  /* USER CODE END 2 */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  HAL_LPTIM_Counter_Start_IT(&hlptim1, 65000);
 8000234:	4a03      	ldr	r2, [pc, #12]	; (8000244 <main+0x24>)
 8000236:	4b04      	ldr	r3, [pc, #16]	; (8000248 <main+0x28>)
 8000238:	0011      	movs	r1, r2
 800023a:	0018      	movs	r0, r3
 800023c:	f000 fb50 	bl	80008e0 <HAL_LPTIM_Counter_Start_IT>

  while (1)
 8000240:	e7fe      	b.n	8000240 <main+0x20>
 8000242:	46c0      	nop			; (mov r8, r8)
 8000244:	0000fde8 	.word	0x0000fde8
 8000248:	20000028 	.word	0x20000028

0800024c <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 800024c:	b590      	push	{r4, r7, lr}
 800024e:	b09f      	sub	sp, #124	; 0x7c
 8000250:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 8000252:	2440      	movs	r4, #64	; 0x40
 8000254:	193b      	adds	r3, r7, r4
 8000256:	0018      	movs	r0, r3
 8000258:	2338      	movs	r3, #56	; 0x38
 800025a:	001a      	movs	r2, r3
 800025c:	2100      	movs	r1, #0
 800025e:	f001 fb91 	bl	8001984 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8000262:	232c      	movs	r3, #44	; 0x2c
 8000264:	18fb      	adds	r3, r7, r3
 8000266:	0018      	movs	r0, r3
 8000268:	2314      	movs	r3, #20
 800026a:	001a      	movs	r2, r3
 800026c:	2100      	movs	r1, #0
 800026e:	f001 fb89 	bl	8001984 <memset>
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8000272:	1d3b      	adds	r3, r7, #4
 8000274:	0018      	movs	r0, r3
 8000276:	2328      	movs	r3, #40	; 0x28
 8000278:	001a      	movs	r2, r3
 800027a:	2100      	movs	r1, #0
 800027c:	f001 fb82 	bl	8001984 <memset>

  /** Configure the main internal regulator output voltage 
  */
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 8000280:	4b2c      	ldr	r3, [pc, #176]	; (8000334 <SystemClock_Config+0xe8>)
 8000282:	681b      	ldr	r3, [r3, #0]
 8000284:	4a2c      	ldr	r2, [pc, #176]	; (8000338 <SystemClock_Config+0xec>)
 8000286:	401a      	ands	r2, r3
 8000288:	4b2a      	ldr	r3, [pc, #168]	; (8000334 <SystemClock_Config+0xe8>)
 800028a:	2180      	movs	r1, #128	; 0x80
 800028c:	0109      	lsls	r1, r1, #4
 800028e:	430a      	orrs	r2, r1
 8000290:	601a      	str	r2, [r3, #0]
  /** Configure LSE Drive Capability 
  */
  HAL_PWR_EnableBkUpAccess();
 8000292:	f000 fc53 	bl	8000b3c <HAL_PWR_EnableBkUpAccess>
  __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
 8000296:	4b29      	ldr	r3, [pc, #164]	; (800033c <SystemClock_Config+0xf0>)
 8000298:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 800029a:	4b28      	ldr	r3, [pc, #160]	; (800033c <SystemClock_Config+0xf0>)
 800029c:	4926      	ldr	r1, [pc, #152]	; (8000338 <SystemClock_Config+0xec>)
 800029e:	400a      	ands	r2, r1
 80002a0:	651a      	str	r2, [r3, #80]	; 0x50
  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
 80002a2:	0021      	movs	r1, r4
 80002a4:	187b      	adds	r3, r7, r1
 80002a6:	2214      	movs	r2, #20
 80002a8:	601a      	str	r2, [r3, #0]
  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
 80002aa:	187b      	adds	r3, r7, r1
 80002ac:	2280      	movs	r2, #128	; 0x80
 80002ae:	0052      	lsls	r2, r2, #1
 80002b0:	609a      	str	r2, [r3, #8]
  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
 80002b2:	187b      	adds	r3, r7, r1
 80002b4:	2201      	movs	r2, #1
 80002b6:	61da      	str	r2, [r3, #28]
  RCC_OscInitStruct.MSICalibrationValue = 0;
 80002b8:	187b      	adds	r3, r7, r1
 80002ba:	2200      	movs	r2, #0
 80002bc:	621a      	str	r2, [r3, #32]
  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5;
 80002be:	187b      	adds	r3, r7, r1
 80002c0:	22a0      	movs	r2, #160	; 0xa0
 80002c2:	0212      	lsls	r2, r2, #8
 80002c4:	625a      	str	r2, [r3, #36]	; 0x24
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
 80002c6:	187b      	adds	r3, r7, r1
 80002c8:	2200      	movs	r2, #0
 80002ca:	629a      	str	r2, [r3, #40]	; 0x28
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 80002cc:	187b      	adds	r3, r7, r1
 80002ce:	0018      	movs	r0, r3
 80002d0:	f000 fc42 	bl	8000b58 <HAL_RCC_OscConfig>
 80002d4:	1e03      	subs	r3, r0, #0
 80002d6:	d001      	beq.n	80002dc <SystemClock_Config+0x90>
  {
    Error_Handler();
 80002d8:	f000 f870 	bl	80003bc <Error_Handler>
  }
  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 80002dc:	212c      	movs	r1, #44	; 0x2c
 80002de:	187b      	adds	r3, r7, r1
 80002e0:	220f      	movs	r2, #15
 80002e2:	601a      	str	r2, [r3, #0]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
 80002e4:	187b      	adds	r3, r7, r1
 80002e6:	2200      	movs	r2, #0
 80002e8:	605a      	str	r2, [r3, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 80002ea:	187b      	adds	r3, r7, r1
 80002ec:	2200      	movs	r2, #0
 80002ee:	609a      	str	r2, [r3, #8]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 80002f0:	187b      	adds	r3, r7, r1
 80002f2:	2200      	movs	r2, #0
 80002f4:	60da      	str	r2, [r3, #12]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 80002f6:	187b      	adds	r3, r7, r1
 80002f8:	2200      	movs	r2, #0
 80002fa:	611a      	str	r2, [r3, #16]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
 80002fc:	187b      	adds	r3, r7, r1
 80002fe:	2100      	movs	r1, #0
 8000300:	0018      	movs	r0, r3
 8000302:	f000 fff9 	bl	80012f8 <HAL_RCC_ClockConfig>
 8000306:	1e03      	subs	r3, r0, #0
 8000308:	d001      	beq.n	800030e <SystemClock_Config+0xc2>
  {
    Error_Handler();
 800030a:	f000 f857 	bl	80003bc <Error_Handler>
  }
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1;
 800030e:	1d3b      	adds	r3, r7, #4
 8000310:	2280      	movs	r2, #128	; 0x80
 8000312:	601a      	str	r2, [r3, #0]
  PeriphClkInit.LptimClockSelection = RCC_LPTIM1CLKSOURCE_LSE;
 8000314:	1d3b      	adds	r3, r7, #4
 8000316:	22c0      	movs	r2, #192	; 0xc0
 8000318:	0312      	lsls	r2, r2, #12
 800031a:	621a      	str	r2, [r3, #32]

  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 800031c:	1d3b      	adds	r3, r7, #4
 800031e:	0018      	movs	r0, r3
 8000320:	f001 f998 	bl	8001654 <HAL_RCCEx_PeriphCLKConfig>
 8000324:	1e03      	subs	r3, r0, #0
 8000326:	d001      	beq.n	800032c <SystemClock_Config+0xe0>
  {
    Error_Handler();
 8000328:	f000 f848 	bl	80003bc <Error_Handler>
  }
}
 800032c:	46c0      	nop			; (mov r8, r8)
 800032e:	46bd      	mov	sp, r7
 8000330:	b01f      	add	sp, #124	; 0x7c
 8000332:	bd90      	pop	{r4, r7, pc}
 8000334:	40007000 	.word	0x40007000
 8000338:	ffffe7ff 	.word	0xffffe7ff
 800033c:	40021000 	.word	0x40021000

08000340 <MX_LPTIM1_Init>:
  * @brief LPTIM1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_LPTIM1_Init(void)
{
 8000340:	b580      	push	{r7, lr}
 8000342:	af00      	add	r7, sp, #0
  /* USER CODE END LPTIM1_Init 0 */

  /* USER CODE BEGIN LPTIM1_Init 1 */

  /* USER CODE END LPTIM1_Init 1 */
  hlptim1.Instance = LPTIM1;
 8000344:	4b0f      	ldr	r3, [pc, #60]	; (8000384 <MX_LPTIM1_Init+0x44>)
 8000346:	4a10      	ldr	r2, [pc, #64]	; (8000388 <MX_LPTIM1_Init+0x48>)
 8000348:	601a      	str	r2, [r3, #0]
  hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
 800034a:	4b0e      	ldr	r3, [pc, #56]	; (8000384 <MX_LPTIM1_Init+0x44>)
 800034c:	2200      	movs	r2, #0
 800034e:	605a      	str	r2, [r3, #4]
  hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1;
 8000350:	4b0c      	ldr	r3, [pc, #48]	; (8000384 <MX_LPTIM1_Init+0x44>)
 8000352:	2200      	movs	r2, #0
 8000354:	609a      	str	r2, [r3, #8]
  hlptim1.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
 8000356:	4b0b      	ldr	r3, [pc, #44]	; (8000384 <MX_LPTIM1_Init+0x44>)
 8000358:	4a0c      	ldr	r2, [pc, #48]	; (800038c <MX_LPTIM1_Init+0x4c>)
 800035a:	615a      	str	r2, [r3, #20]
  hlptim1.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH;
 800035c:	4b09      	ldr	r3, [pc, #36]	; (8000384 <MX_LPTIM1_Init+0x44>)
 800035e:	2200      	movs	r2, #0
 8000360:	621a      	str	r2, [r3, #32]
  hlptim1.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;
 8000362:	4b08      	ldr	r3, [pc, #32]	; (8000384 <MX_LPTIM1_Init+0x44>)
 8000364:	2200      	movs	r2, #0
 8000366:	625a      	str	r2, [r3, #36]	; 0x24
  hlptim1.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL;
 8000368:	4b06      	ldr	r3, [pc, #24]	; (8000384 <MX_LPTIM1_Init+0x44>)
 800036a:	2200      	movs	r2, #0
 800036c:	629a      	str	r2, [r3, #40]	; 0x28
  if (HAL_LPTIM_Init(&hlptim1) != HAL_OK)
 800036e:	4b05      	ldr	r3, [pc, #20]	; (8000384 <MX_LPTIM1_Init+0x44>)
 8000370:	0018      	movs	r0, r3
 8000372:	f000 fa35 	bl	80007e0 <HAL_LPTIM_Init>
 8000376:	1e03      	subs	r3, r0, #0
 8000378:	d001      	beq.n	800037e <MX_LPTIM1_Init+0x3e>
  {
    Error_Handler();
 800037a:	f000 f81f 	bl	80003bc <Error_Handler>
  }
  /* USER CODE BEGIN LPTIM1_Init 2 */

  /* USER CODE END LPTIM1_Init 2 */

}
 800037e:	46c0      	nop			; (mov r8, r8)
 8000380:	46bd      	mov	sp, r7
 8000382:	bd80      	pop	{r7, pc}
 8000384:	20000028 	.word	0x20000028
 8000388:	40007c00 	.word	0x40007c00
 800038c:	0000ffff 	.word	0x0000ffff

08000390 <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 8000390:	b580      	push	{r7, lr}
 8000392:	b082      	sub	sp, #8
 8000394:	af00      	add	r7, sp, #0

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8000396:	4b08      	ldr	r3, [pc, #32]	; (80003b8 <MX_GPIO_Init+0x28>)
 8000398:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 800039a:	4b07      	ldr	r3, [pc, #28]	; (80003b8 <MX_GPIO_Init+0x28>)
 800039c:	2104      	movs	r1, #4
 800039e:	430a      	orrs	r2, r1
 80003a0:	62da      	str	r2, [r3, #44]	; 0x2c
 80003a2:	4b05      	ldr	r3, [pc, #20]	; (80003b8 <MX_GPIO_Init+0x28>)
 80003a4:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80003a6:	2204      	movs	r2, #4
 80003a8:	4013      	ands	r3, r2
 80003aa:	607b      	str	r3, [r7, #4]
 80003ac:	687b      	ldr	r3, [r7, #4]

}
 80003ae:	46c0      	nop			; (mov r8, r8)
 80003b0:	46bd      	mov	sp, r7
 80003b2:	b002      	add	sp, #8
 80003b4:	bd80      	pop	{r7, pc}
 80003b6:	46c0      	nop			; (mov r8, r8)
 80003b8:	40021000 	.word	0x40021000

080003bc <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 80003bc:	b580      	push	{r7, lr}
 80003be:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */

  /* USER CODE END Error_Handler_Debug */
}
 80003c0:	46c0      	nop			; (mov r8, r8)
 80003c2:	46bd      	mov	sp, r7
 80003c4:	bd80      	pop	{r7, pc}
	...

080003c8 <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 80003c8:	b580      	push	{r7, lr}
 80003ca:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 80003cc:	4b07      	ldr	r3, [pc, #28]	; (80003ec <HAL_MspInit+0x24>)
 80003ce:	6b5a      	ldr	r2, [r3, #52]	; 0x34
 80003d0:	4b06      	ldr	r3, [pc, #24]	; (80003ec <HAL_MspInit+0x24>)
 80003d2:	2101      	movs	r1, #1
 80003d4:	430a      	orrs	r2, r1
 80003d6:	635a      	str	r2, [r3, #52]	; 0x34
  __HAL_RCC_PWR_CLK_ENABLE();
 80003d8:	4b04      	ldr	r3, [pc, #16]	; (80003ec <HAL_MspInit+0x24>)
 80003da:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 80003dc:	4b03      	ldr	r3, [pc, #12]	; (80003ec <HAL_MspInit+0x24>)
 80003de:	2180      	movs	r1, #128	; 0x80
 80003e0:	0549      	lsls	r1, r1, #21
 80003e2:	430a      	orrs	r2, r1
 80003e4:	639a      	str	r2, [r3, #56]	; 0x38
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 80003e6:	46c0      	nop			; (mov r8, r8)
 80003e8:	46bd      	mov	sp, r7
 80003ea:	bd80      	pop	{r7, pc}
 80003ec:	40021000 	.word	0x40021000

080003f0 <HAL_LPTIM_MspInit>:
* This function configures the hardware resources used in this example
* @param hlptim: LPTIM handle pointer
* @retval None
*/
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef* hlptim)
{
 80003f0:	b580      	push	{r7, lr}
 80003f2:	b082      	sub	sp, #8
 80003f4:	af00      	add	r7, sp, #0
 80003f6:	6078      	str	r0, [r7, #4]
  if(hlptim->Instance==LPTIM1)
 80003f8:	687b      	ldr	r3, [r7, #4]
 80003fa:	681b      	ldr	r3, [r3, #0]
 80003fc:	4a0a      	ldr	r2, [pc, #40]	; (8000428 <HAL_LPTIM_MspInit+0x38>)
 80003fe:	4293      	cmp	r3, r2
 8000400:	d10e      	bne.n	8000420 <HAL_LPTIM_MspInit+0x30>
  {
  /* USER CODE BEGIN LPTIM1_MspInit 0 */

  /* USER CODE END LPTIM1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_LPTIM1_CLK_ENABLE();
 8000402:	4b0a      	ldr	r3, [pc, #40]	; (800042c <HAL_LPTIM_MspInit+0x3c>)
 8000404:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 8000406:	4b09      	ldr	r3, [pc, #36]	; (800042c <HAL_LPTIM_MspInit+0x3c>)
 8000408:	2180      	movs	r1, #128	; 0x80
 800040a:	0609      	lsls	r1, r1, #24
 800040c:	430a      	orrs	r2, r1
 800040e:	639a      	str	r2, [r3, #56]	; 0x38
    /* LPTIM1 interrupt Init */
    HAL_NVIC_SetPriority(LPTIM1_IRQn, 0, 0);
 8000410:	2200      	movs	r2, #0
 8000412:	2100      	movs	r1, #0
 8000414:	200d      	movs	r0, #13
 8000416:	f000 f9b1 	bl	800077c <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(LPTIM1_IRQn);
 800041a:	200d      	movs	r0, #13
 800041c:	f000 f9c3 	bl	80007a6 <HAL_NVIC_EnableIRQ>
  /* USER CODE BEGIN LPTIM1_MspInit 1 */

  /* USER CODE END LPTIM1_MspInit 1 */
  }

}
 8000420:	46c0      	nop			; (mov r8, r8)
 8000422:	46bd      	mov	sp, r7
 8000424:	b002      	add	sp, #8
 8000426:	bd80      	pop	{r7, pc}
 8000428:	40007c00 	.word	0x40007c00
 800042c:	40021000 	.word	0x40021000

08000430 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable Interrupt.
  */
void NMI_Handler(void)
{
 8000430:	b580      	push	{r7, lr}
 8000432:	af00      	add	r7, sp, #0

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */

  /* USER CODE END NonMaskableInt_IRQn 1 */
}
 8000434:	46c0      	nop			; (mov r8, r8)
 8000436:	46bd      	mov	sp, r7
 8000438:	bd80      	pop	{r7, pc}

0800043a <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 800043a:	b580      	push	{r7, lr}
 800043c:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 800043e:	e7fe      	b.n	800043e <HardFault_Handler+0x4>

08000440 <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 8000440:	b580      	push	{r7, lr}
 8000442:	af00      	add	r7, sp, #0

  /* USER CODE END SVC_IRQn 0 */
  /* USER CODE BEGIN SVC_IRQn 1 */

  /* USER CODE END SVC_IRQn 1 */
}
 8000444:	46c0      	nop			; (mov r8, r8)
 8000446:	46bd      	mov	sp, r7
 8000448:	bd80      	pop	{r7, pc}

0800044a <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 800044a:	b580      	push	{r7, lr}
 800044c:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 800044e:	46c0      	nop			; (mov r8, r8)
 8000450:	46bd      	mov	sp, r7
 8000452:	bd80      	pop	{r7, pc}

08000454 <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 8000454:	b580      	push	{r7, lr}
 8000456:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8000458:	f000 f8cc 	bl	80005f4 <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 800045c:	46c0      	nop			; (mov r8, r8)
 800045e:	46bd      	mov	sp, r7
 8000460:	bd80      	pop	{r7, pc}
	...

08000464 <LPTIM1_IRQHandler>:

/**
  * @brief This function handles LPTIM1 global interrupt / LPTIM1 wake-up interrupt through EXTI line 29.
  */
void LPTIM1_IRQHandler(void)
{
 8000464:	b580      	push	{r7, lr}
 8000466:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN LPTIM1_IRQn 0 */

  /* USER CODE END LPTIM1_IRQn 0 */
  HAL_LPTIM_IRQHandler(&hlptim1);
 8000468:	4b03      	ldr	r3, [pc, #12]	; (8000478 <LPTIM1_IRQHandler+0x14>)
 800046a:	0018      	movs	r0, r3
 800046c:	f000 fa8c 	bl	8000988 <HAL_LPTIM_IRQHandler>
  /* USER CODE BEGIN LPTIM1_IRQn 1 */

  /* USER CODE END LPTIM1_IRQn 1 */
}
 8000470:	46c0      	nop			; (mov r8, r8)
 8000472:	46bd      	mov	sp, r7
 8000474:	bd80      	pop	{r7, pc}
 8000476:	46c0      	nop			; (mov r8, r8)
 8000478:	20000028 	.word	0x20000028

0800047c <SystemInit>:
  * @brief  Setup the microcontroller system.
  * @param  None
  * @retval None
  */
void SystemInit (void)
{
 800047c:	b580      	push	{r7, lr}
 800047e:	af00      	add	r7, sp, #0
/*!< Set MSION bit */
  RCC->CR |= (uint32_t)0x00000100U;
 8000480:	4b17      	ldr	r3, [pc, #92]	; (80004e0 <SystemInit+0x64>)
 8000482:	681a      	ldr	r2, [r3, #0]
 8000484:	4b16      	ldr	r3, [pc, #88]	; (80004e0 <SystemInit+0x64>)
 8000486:	2180      	movs	r1, #128	; 0x80
 8000488:	0049      	lsls	r1, r1, #1
 800048a:	430a      	orrs	r2, r1
 800048c:	601a      	str	r2, [r3, #0]

  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
  RCC->CFGR &= (uint32_t) 0x88FF400CU;
 800048e:	4b14      	ldr	r3, [pc, #80]	; (80004e0 <SystemInit+0x64>)
 8000490:	68da      	ldr	r2, [r3, #12]
 8000492:	4b13      	ldr	r3, [pc, #76]	; (80004e0 <SystemInit+0x64>)
 8000494:	4913      	ldr	r1, [pc, #76]	; (80004e4 <SystemInit+0x68>)
 8000496:	400a      	ands	r2, r1
 8000498:	60da      	str	r2, [r3, #12]

  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
  RCC->CR &= (uint32_t)0xFEF6FFF6U;
 800049a:	4b11      	ldr	r3, [pc, #68]	; (80004e0 <SystemInit+0x64>)
 800049c:	681a      	ldr	r2, [r3, #0]
 800049e:	4b10      	ldr	r3, [pc, #64]	; (80004e0 <SystemInit+0x64>)
 80004a0:	4911      	ldr	r1, [pc, #68]	; (80004e8 <SystemInit+0x6c>)
 80004a2:	400a      	ands	r2, r1
 80004a4:	601a      	str	r2, [r3, #0]

  /*!< Reset HSI48ON  bit */
  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
 80004a6:	4b0e      	ldr	r3, [pc, #56]	; (80004e0 <SystemInit+0x64>)
 80004a8:	689a      	ldr	r2, [r3, #8]
 80004aa:	4b0d      	ldr	r3, [pc, #52]	; (80004e0 <SystemInit+0x64>)
 80004ac:	2101      	movs	r1, #1
 80004ae:	438a      	bics	r2, r1
 80004b0:	609a      	str	r2, [r3, #8]

  /*!< Reset HSEBYP bit */
  RCC->CR &= (uint32_t)0xFFFBFFFFU;
 80004b2:	4b0b      	ldr	r3, [pc, #44]	; (80004e0 <SystemInit+0x64>)
 80004b4:	681a      	ldr	r2, [r3, #0]
 80004b6:	4b0a      	ldr	r3, [pc, #40]	; (80004e0 <SystemInit+0x64>)
 80004b8:	490c      	ldr	r1, [pc, #48]	; (80004ec <SystemInit+0x70>)
 80004ba:	400a      	ands	r2, r1
 80004bc:	601a      	str	r2, [r3, #0]

  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
 80004be:	4b08      	ldr	r3, [pc, #32]	; (80004e0 <SystemInit+0x64>)
 80004c0:	68da      	ldr	r2, [r3, #12]
 80004c2:	4b07      	ldr	r3, [pc, #28]	; (80004e0 <SystemInit+0x64>)
 80004c4:	490a      	ldr	r1, [pc, #40]	; (80004f0 <SystemInit+0x74>)
 80004c6:	400a      	ands	r2, r1
 80004c8:	60da      	str	r2, [r3, #12]

  /*!< Disable all interrupts */
  RCC->CIER = 0x00000000U;
 80004ca:	4b05      	ldr	r3, [pc, #20]	; (80004e0 <SystemInit+0x64>)
 80004cc:	2200      	movs	r2, #0
 80004ce:	611a      	str	r2, [r3, #16]

  /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 80004d0:	4b08      	ldr	r3, [pc, #32]	; (80004f4 <SystemInit+0x78>)
 80004d2:	2280      	movs	r2, #128	; 0x80
 80004d4:	0512      	lsls	r2, r2, #20
 80004d6:	609a      	str	r2, [r3, #8]
#endif
}
 80004d8:	46c0      	nop			; (mov r8, r8)
 80004da:	46bd      	mov	sp, r7
 80004dc:	bd80      	pop	{r7, pc}
 80004de:	46c0      	nop			; (mov r8, r8)
 80004e0:	40021000 	.word	0x40021000
 80004e4:	88ff400c 	.word	0x88ff400c
 80004e8:	fef6fff6 	.word	0xfef6fff6
 80004ec:	fffbffff 	.word	0xfffbffff
 80004f0:	ff02ffff 	.word	0xff02ffff
 80004f4:	e000ed00 	.word	0xe000ed00

080004f8 <Reset_Handler>:

    .section  .text.Reset_Handler
  .weak  Reset_Handler
  .type  Reset_Handler, %function
Reset_Handler:  
   ldr   r0, =_estack
 80004f8:	480d      	ldr	r0, [pc, #52]	; (8000530 <LoopForever+0x2>)
   mov   sp, r0          /* set stack pointer */
 80004fa:	4685      	mov	sp, r0

/* Copy the data segment initializers from flash to SRAM */
  movs  r1, #0
 80004fc:	2100      	movs	r1, #0
  b  LoopCopyDataInit
 80004fe:	e003      	b.n	8000508 <LoopCopyDataInit>

08000500 <CopyDataInit>:

CopyDataInit:
  ldr  r3, =_sidata
 8000500:	4b0c      	ldr	r3, [pc, #48]	; (8000534 <LoopForever+0x6>)
  ldr  r3, [r3, r1]
 8000502:	585b      	ldr	r3, [r3, r1]
  str  r3, [r0, r1]
 8000504:	5043      	str	r3, [r0, r1]
  adds  r1, r1, #4
 8000506:	3104      	adds	r1, #4

08000508 <LoopCopyDataInit>:

LoopCopyDataInit:
  ldr  r0, =_sdata
 8000508:	480b      	ldr	r0, [pc, #44]	; (8000538 <LoopForever+0xa>)
  ldr  r3, =_edata
 800050a:	4b0c      	ldr	r3, [pc, #48]	; (800053c <LoopForever+0xe>)
  adds  r2, r0, r1
 800050c:	1842      	adds	r2, r0, r1
  cmp  r2, r3
 800050e:	429a      	cmp	r2, r3
  bcc  CopyDataInit
 8000510:	d3f6      	bcc.n	8000500 <CopyDataInit>
  ldr  r2, =_sbss
 8000512:	4a0b      	ldr	r2, [pc, #44]	; (8000540 <LoopForever+0x12>)
  b  LoopFillZerobss
 8000514:	e002      	b.n	800051c <LoopFillZerobss>

08000516 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
  movs  r3, #0
 8000516:	2300      	movs	r3, #0
  str  r3, [r2]
 8000518:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 800051a:	3204      	adds	r2, #4

0800051c <LoopFillZerobss>:


LoopFillZerobss:
  ldr  r3, = _ebss
 800051c:	4b09      	ldr	r3, [pc, #36]	; (8000544 <LoopForever+0x16>)
  cmp  r2, r3
 800051e:	429a      	cmp	r2, r3
  bcc  FillZerobss
 8000520:	d3f9      	bcc.n	8000516 <FillZerobss>

/* Call the clock system intitialization function.*/
  bl  SystemInit
 8000522:	f7ff ffab 	bl	800047c <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 8000526:	f001 fa09 	bl	800193c <__libc_init_array>
/* Call the application's entry point.*/
  bl  main
 800052a:	f7ff fe79 	bl	8000220 <main>

0800052e <LoopForever>:

LoopForever:
    b LoopForever
 800052e:	e7fe      	b.n	800052e <LoopForever>
   ldr   r0, =_estack
 8000530:	20005000 	.word	0x20005000
  ldr  r3, =_sidata
 8000534:	080019d0 	.word	0x080019d0
  ldr  r0, =_sdata
 8000538:	20000000 	.word	0x20000000
  ldr  r3, =_edata
 800053c:	2000000c 	.word	0x2000000c
  ldr  r2, =_sbss
 8000540:	2000000c 	.word	0x2000000c
  ldr  r3, = _ebss
 8000544:	2000005c 	.word	0x2000005c

08000548 <ADC1_COMP_IRQHandler>:
 * @retval : None
*/
    .section  .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b  Infinite_Loop
 8000548:	e7fe      	b.n	8000548 <ADC1_COMP_IRQHandler>
	...

0800054c <HAL_Init>:
  *        In the default implementation,Systick is used as source of time base.
  *        the tick variable is incremented each 1ms in its ISR.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 800054c:	b580      	push	{r7, lr}
 800054e:	b082      	sub	sp, #8
 8000550:	af00      	add	r7, sp, #0
  HAL_StatusTypeDef  status = HAL_OK;
 8000552:	1dfb      	adds	r3, r7, #7
 8000554:	2200      	movs	r2, #0
 8000556:	701a      	strb	r2, [r3, #0]
#if (BUFFER_CACHE_DISABLE != 0)
  __HAL_FLASH_BUFFER_CACHE_DISABLE();
#endif /* BUFFER_CACHE_DISABLE */

#if (PREREAD_ENABLE != 0)
  __HAL_FLASH_PREREAD_BUFFER_ENABLE();
 8000558:	4b0b      	ldr	r3, [pc, #44]	; (8000588 <HAL_Init+0x3c>)
 800055a:	681a      	ldr	r2, [r3, #0]
 800055c:	4b0a      	ldr	r3, [pc, #40]	; (8000588 <HAL_Init+0x3c>)
 800055e:	2140      	movs	r1, #64	; 0x40
 8000560:	430a      	orrs	r2, r1
 8000562:	601a      	str	r2, [r3, #0]
#if (PREFETCH_ENABLE != 0)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */

  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 8000564:	2000      	movs	r0, #0
 8000566:	f000 f811 	bl	800058c <HAL_InitTick>
 800056a:	1e03      	subs	r3, r0, #0
 800056c:	d003      	beq.n	8000576 <HAL_Init+0x2a>
  {
    status = HAL_ERROR;
 800056e:	1dfb      	adds	r3, r7, #7
 8000570:	2201      	movs	r2, #1
 8000572:	701a      	strb	r2, [r3, #0]
 8000574:	e001      	b.n	800057a <HAL_Init+0x2e>
  }
  else
  {
    /* Init the low level hardware */
    HAL_MspInit();
 8000576:	f7ff ff27 	bl	80003c8 <HAL_MspInit>
  }

  /* Return function status */
  return status;
 800057a:	1dfb      	adds	r3, r7, #7
 800057c:	781b      	ldrb	r3, [r3, #0]
}
 800057e:	0018      	movs	r0, r3
 8000580:	46bd      	mov	sp, r7
 8000582:	b002      	add	sp, #8
 8000584:	bd80      	pop	{r7, pc}
 8000586:	46c0      	nop			; (mov r8, r8)
 8000588:	40022000 	.word	0x40022000

0800058c <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 800058c:	b590      	push	{r4, r7, lr}
 800058e:	b083      	sub	sp, #12
 8000590:	af00      	add	r7, sp, #0
 8000592:	6078      	str	r0, [r7, #4]
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 8000594:	4b14      	ldr	r3, [pc, #80]	; (80005e8 <HAL_InitTick+0x5c>)
 8000596:	681c      	ldr	r4, [r3, #0]
 8000598:	4b14      	ldr	r3, [pc, #80]	; (80005ec <HAL_InitTick+0x60>)
 800059a:	781b      	ldrb	r3, [r3, #0]
 800059c:	0019      	movs	r1, r3
 800059e:	23fa      	movs	r3, #250	; 0xfa
 80005a0:	0098      	lsls	r0, r3, #2
 80005a2:	f7ff fdb1 	bl	8000108 <__udivsi3>
 80005a6:	0003      	movs	r3, r0
 80005a8:	0019      	movs	r1, r3
 80005aa:	0020      	movs	r0, r4
 80005ac:	f7ff fdac 	bl	8000108 <__udivsi3>
 80005b0:	0003      	movs	r3, r0
 80005b2:	0018      	movs	r0, r3
 80005b4:	f000 f907 	bl	80007c6 <HAL_SYSTICK_Config>
 80005b8:	1e03      	subs	r3, r0, #0
 80005ba:	d001      	beq.n	80005c0 <HAL_InitTick+0x34>
  {
    return HAL_ERROR;
 80005bc:	2301      	movs	r3, #1
 80005be:	e00f      	b.n	80005e0 <HAL_InitTick+0x54>
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 80005c0:	687b      	ldr	r3, [r7, #4]
 80005c2:	2b03      	cmp	r3, #3
 80005c4:	d80b      	bhi.n	80005de <HAL_InitTick+0x52>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 80005c6:	6879      	ldr	r1, [r7, #4]
 80005c8:	2301      	movs	r3, #1
 80005ca:	425b      	negs	r3, r3
 80005cc:	2200      	movs	r2, #0
 80005ce:	0018      	movs	r0, r3
 80005d0:	f000 f8d4 	bl	800077c <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 80005d4:	4b06      	ldr	r3, [pc, #24]	; (80005f0 <HAL_InitTick+0x64>)
 80005d6:	687a      	ldr	r2, [r7, #4]
 80005d8:	601a      	str	r2, [r3, #0]
  {
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
 80005da:	2300      	movs	r3, #0
 80005dc:	e000      	b.n	80005e0 <HAL_InitTick+0x54>
    return HAL_ERROR;
 80005de:	2301      	movs	r3, #1
}
 80005e0:	0018      	movs	r0, r3
 80005e2:	46bd      	mov	sp, r7
 80005e4:	b003      	add	sp, #12
 80005e6:	bd90      	pop	{r4, r7, pc}
 80005e8:	20000000 	.word	0x20000000
 80005ec:	20000008 	.word	0x20000008
 80005f0:	20000004 	.word	0x20000004

080005f4 <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 80005f4:	b580      	push	{r7, lr}
 80005f6:	af00      	add	r7, sp, #0
  uwTick += uwTickFreq;
 80005f8:	4b05      	ldr	r3, [pc, #20]	; (8000610 <HAL_IncTick+0x1c>)
 80005fa:	781b      	ldrb	r3, [r3, #0]
 80005fc:	001a      	movs	r2, r3
 80005fe:	4b05      	ldr	r3, [pc, #20]	; (8000614 <HAL_IncTick+0x20>)
 8000600:	681b      	ldr	r3, [r3, #0]
 8000602:	18d2      	adds	r2, r2, r3
 8000604:	4b03      	ldr	r3, [pc, #12]	; (8000614 <HAL_IncTick+0x20>)
 8000606:	601a      	str	r2, [r3, #0]
}
 8000608:	46c0      	nop			; (mov r8, r8)
 800060a:	46bd      	mov	sp, r7
 800060c:	bd80      	pop	{r7, pc}
 800060e:	46c0      	nop			; (mov r8, r8)
 8000610:	20000008 	.word	0x20000008
 8000614:	20000058 	.word	0x20000058

08000618 <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 8000618:	b580      	push	{r7, lr}
 800061a:	af00      	add	r7, sp, #0
  return uwTick;
 800061c:	4b02      	ldr	r3, [pc, #8]	; (8000628 <HAL_GetTick+0x10>)
 800061e:	681b      	ldr	r3, [r3, #0]
}
 8000620:	0018      	movs	r0, r3
 8000622:	46bd      	mov	sp, r7
 8000624:	bd80      	pop	{r7, pc}
 8000626:	46c0      	nop			; (mov r8, r8)
 8000628:	20000058 	.word	0x20000058

0800062c <NVIC_EnableIRQ>:
  \brief   Enable External Interrupt
  \details Enables a device-specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
 800062c:	b580      	push	{r7, lr}
 800062e:	b082      	sub	sp, #8
 8000630:	af00      	add	r7, sp, #0
 8000632:	0002      	movs	r2, r0
 8000634:	1dfb      	adds	r3, r7, #7
 8000636:	701a      	strb	r2, [r3, #0]
  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 8000638:	1dfb      	adds	r3, r7, #7
 800063a:	781b      	ldrb	r3, [r3, #0]
 800063c:	001a      	movs	r2, r3
 800063e:	231f      	movs	r3, #31
 8000640:	401a      	ands	r2, r3
 8000642:	4b04      	ldr	r3, [pc, #16]	; (8000654 <NVIC_EnableIRQ+0x28>)
 8000644:	2101      	movs	r1, #1
 8000646:	4091      	lsls	r1, r2
 8000648:	000a      	movs	r2, r1
 800064a:	601a      	str	r2, [r3, #0]
}
 800064c:	46c0      	nop			; (mov r8, r8)
 800064e:	46bd      	mov	sp, r7
 8000650:	b002      	add	sp, #8
 8000652:	bd80      	pop	{r7, pc}
 8000654:	e000e100 	.word	0xe000e100

08000658 <NVIC_SetPriority>:
  \note    The priority cannot be set for every core interrupt.
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
 */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 8000658:	b590      	push	{r4, r7, lr}
 800065a:	b083      	sub	sp, #12
 800065c:	af00      	add	r7, sp, #0
 800065e:	0002      	movs	r2, r0
 8000660:	6039      	str	r1, [r7, #0]
 8000662:	1dfb      	adds	r3, r7, #7
 8000664:	701a      	strb	r2, [r3, #0]
  if ((int32_t)(IRQn) < 0)
 8000666:	1dfb      	adds	r3, r7, #7
 8000668:	781b      	ldrb	r3, [r3, #0]
 800066a:	2b7f      	cmp	r3, #127	; 0x7f
 800066c:	d932      	bls.n	80006d4 <NVIC_SetPriority+0x7c>
  {
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 800066e:	4a2f      	ldr	r2, [pc, #188]	; (800072c <NVIC_SetPriority+0xd4>)
 8000670:	1dfb      	adds	r3, r7, #7
 8000672:	781b      	ldrb	r3, [r3, #0]
 8000674:	0019      	movs	r1, r3
 8000676:	230f      	movs	r3, #15
 8000678:	400b      	ands	r3, r1
 800067a:	3b08      	subs	r3, #8
 800067c:	089b      	lsrs	r3, r3, #2
 800067e:	3306      	adds	r3, #6
 8000680:	009b      	lsls	r3, r3, #2
 8000682:	18d3      	adds	r3, r2, r3
 8000684:	3304      	adds	r3, #4
 8000686:	681b      	ldr	r3, [r3, #0]
 8000688:	1dfa      	adds	r2, r7, #7
 800068a:	7812      	ldrb	r2, [r2, #0]
 800068c:	0011      	movs	r1, r2
 800068e:	2203      	movs	r2, #3
 8000690:	400a      	ands	r2, r1
 8000692:	00d2      	lsls	r2, r2, #3
 8000694:	21ff      	movs	r1, #255	; 0xff
 8000696:	4091      	lsls	r1, r2
 8000698:	000a      	movs	r2, r1
 800069a:	43d2      	mvns	r2, r2
 800069c:	401a      	ands	r2, r3
 800069e:	0011      	movs	r1, r2
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 80006a0:	683b      	ldr	r3, [r7, #0]
 80006a2:	019b      	lsls	r3, r3, #6
 80006a4:	22ff      	movs	r2, #255	; 0xff
 80006a6:	401a      	ands	r2, r3
 80006a8:	1dfb      	adds	r3, r7, #7
 80006aa:	781b      	ldrb	r3, [r3, #0]
 80006ac:	0018      	movs	r0, r3
 80006ae:	2303      	movs	r3, #3
 80006b0:	4003      	ands	r3, r0
 80006b2:	00db      	lsls	r3, r3, #3
 80006b4:	409a      	lsls	r2, r3
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 80006b6:	481d      	ldr	r0, [pc, #116]	; (800072c <NVIC_SetPriority+0xd4>)
 80006b8:	1dfb      	adds	r3, r7, #7
 80006ba:	781b      	ldrb	r3, [r3, #0]
 80006bc:	001c      	movs	r4, r3
 80006be:	230f      	movs	r3, #15
 80006c0:	4023      	ands	r3, r4
 80006c2:	3b08      	subs	r3, #8
 80006c4:	089b      	lsrs	r3, r3, #2
 80006c6:	430a      	orrs	r2, r1
 80006c8:	3306      	adds	r3, #6
 80006ca:	009b      	lsls	r3, r3, #2
 80006cc:	18c3      	adds	r3, r0, r3
 80006ce:	3304      	adds	r3, #4
 80006d0:	601a      	str	r2, [r3, #0]
  else
  {
    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  }
}
 80006d2:	e027      	b.n	8000724 <NVIC_SetPriority+0xcc>
    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 80006d4:	4a16      	ldr	r2, [pc, #88]	; (8000730 <NVIC_SetPriority+0xd8>)
 80006d6:	1dfb      	adds	r3, r7, #7
 80006d8:	781b      	ldrb	r3, [r3, #0]
 80006da:	b25b      	sxtb	r3, r3
 80006dc:	089b      	lsrs	r3, r3, #2
 80006de:	33c0      	adds	r3, #192	; 0xc0
 80006e0:	009b      	lsls	r3, r3, #2
 80006e2:	589b      	ldr	r3, [r3, r2]
 80006e4:	1dfa      	adds	r2, r7, #7
 80006e6:	7812      	ldrb	r2, [r2, #0]
 80006e8:	0011      	movs	r1, r2
 80006ea:	2203      	movs	r2, #3
 80006ec:	400a      	ands	r2, r1
 80006ee:	00d2      	lsls	r2, r2, #3
 80006f0:	21ff      	movs	r1, #255	; 0xff
 80006f2:	4091      	lsls	r1, r2
 80006f4:	000a      	movs	r2, r1
 80006f6:	43d2      	mvns	r2, r2
 80006f8:	401a      	ands	r2, r3
 80006fa:	0011      	movs	r1, r2
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 80006fc:	683b      	ldr	r3, [r7, #0]
 80006fe:	019b      	lsls	r3, r3, #6
 8000700:	22ff      	movs	r2, #255	; 0xff
 8000702:	401a      	ands	r2, r3
 8000704:	1dfb      	adds	r3, r7, #7
 8000706:	781b      	ldrb	r3, [r3, #0]
 8000708:	0018      	movs	r0, r3
 800070a:	2303      	movs	r3, #3
 800070c:	4003      	ands	r3, r0
 800070e:	00db      	lsls	r3, r3, #3
 8000710:	409a      	lsls	r2, r3
    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 8000712:	4807      	ldr	r0, [pc, #28]	; (8000730 <NVIC_SetPriority+0xd8>)
 8000714:	1dfb      	adds	r3, r7, #7
 8000716:	781b      	ldrb	r3, [r3, #0]
 8000718:	b25b      	sxtb	r3, r3
 800071a:	089b      	lsrs	r3, r3, #2
 800071c:	430a      	orrs	r2, r1
 800071e:	33c0      	adds	r3, #192	; 0xc0
 8000720:	009b      	lsls	r3, r3, #2
 8000722:	501a      	str	r2, [r3, r0]
}
 8000724:	46c0      	nop			; (mov r8, r8)
 8000726:	46bd      	mov	sp, r7
 8000728:	b003      	add	sp, #12
 800072a:	bd90      	pop	{r4, r7, pc}
 800072c:	e000ed00 	.word	0xe000ed00
 8000730:	e000e100 	.word	0xe000e100

08000734 <SysTick_Config>:
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
 8000734:	b580      	push	{r7, lr}
 8000736:	b082      	sub	sp, #8
 8000738:	af00      	add	r7, sp, #0
 800073a:	6078      	str	r0, [r7, #4]
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 800073c:	687b      	ldr	r3, [r7, #4]
 800073e:	3b01      	subs	r3, #1
 8000740:	4a0c      	ldr	r2, [pc, #48]	; (8000774 <SysTick_Config+0x40>)
 8000742:	4293      	cmp	r3, r2
 8000744:	d901      	bls.n	800074a <SysTick_Config+0x16>
  {
    return (1UL);                                                   /* Reload value impossible */
 8000746:	2301      	movs	r3, #1
 8000748:	e010      	b.n	800076c <SysTick_Config+0x38>
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 800074a:	4b0b      	ldr	r3, [pc, #44]	; (8000778 <SysTick_Config+0x44>)
 800074c:	687a      	ldr	r2, [r7, #4]
 800074e:	3a01      	subs	r2, #1
 8000750:	605a      	str	r2, [r3, #4]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 8000752:	2301      	movs	r3, #1
 8000754:	425b      	negs	r3, r3
 8000756:	2103      	movs	r1, #3
 8000758:	0018      	movs	r0, r3
 800075a:	f7ff ff7d 	bl	8000658 <NVIC_SetPriority>
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 800075e:	4b06      	ldr	r3, [pc, #24]	; (8000778 <SysTick_Config+0x44>)
 8000760:	2200      	movs	r2, #0
 8000762:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 8000764:	4b04      	ldr	r3, [pc, #16]	; (8000778 <SysTick_Config+0x44>)
 8000766:	2207      	movs	r2, #7
 8000768:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 800076a:	2300      	movs	r3, #0
}
 800076c:	0018      	movs	r0, r3
 800076e:	46bd      	mov	sp, r7
 8000770:	b002      	add	sp, #8
 8000772:	bd80      	pop	{r7, pc}
 8000774:	00ffffff 	.word	0x00ffffff
 8000778:	e000e010 	.word	0xe000e010

0800077c <HAL_NVIC_SetPriority>:
  *         with stm32l0xx devices, this parameter is a dummy value and it is ignored, because 
  *         no subpriority supported in Cortex M0+ based products.   
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 800077c:	b580      	push	{r7, lr}
 800077e:	b084      	sub	sp, #16
 8000780:	af00      	add	r7, sp, #0
 8000782:	60b9      	str	r1, [r7, #8]
 8000784:	607a      	str	r2, [r7, #4]
 8000786:	210f      	movs	r1, #15
 8000788:	187b      	adds	r3, r7, r1
 800078a:	1c02      	adds	r2, r0, #0
 800078c:	701a      	strb	r2, [r3, #0]
    /* Check the parameters */
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  NVIC_SetPriority(IRQn,PreemptPriority);
 800078e:	68ba      	ldr	r2, [r7, #8]
 8000790:	187b      	adds	r3, r7, r1
 8000792:	781b      	ldrb	r3, [r3, #0]
 8000794:	b25b      	sxtb	r3, r3
 8000796:	0011      	movs	r1, r2
 8000798:	0018      	movs	r0, r3
 800079a:	f7ff ff5d 	bl	8000658 <NVIC_SetPriority>
}
 800079e:	46c0      	nop			; (mov r8, r8)
 80007a0:	46bd      	mov	sp, r7
 80007a2:	b004      	add	sp, #16
 80007a4:	bd80      	pop	{r7, pc}

080007a6 <HAL_NVIC_EnableIRQ>:
  *         This parameter can be an enumerator of  IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)  
  * @retval None
  */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
 80007a6:	b580      	push	{r7, lr}
 80007a8:	b082      	sub	sp, #8
 80007aa:	af00      	add	r7, sp, #0
 80007ac:	0002      	movs	r2, r0
 80007ae:	1dfb      	adds	r3, r7, #7
 80007b0:	701a      	strb	r2, [r3, #0]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  
  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
 80007b2:	1dfb      	adds	r3, r7, #7
 80007b4:	781b      	ldrb	r3, [r3, #0]
 80007b6:	b25b      	sxtb	r3, r3
 80007b8:	0018      	movs	r0, r3
 80007ba:	f7ff ff37 	bl	800062c <NVIC_EnableIRQ>
}
 80007be:	46c0      	nop			; (mov r8, r8)
 80007c0:	46bd      	mov	sp, r7
 80007c2:	b002      	add	sp, #8
 80007c4:	bd80      	pop	{r7, pc}

080007c6 <HAL_SYSTICK_Config>:
  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 80007c6:	b580      	push	{r7, lr}
 80007c8:	b082      	sub	sp, #8
 80007ca:	af00      	add	r7, sp, #0
 80007cc:	6078      	str	r0, [r7, #4]
   return SysTick_Config(TicksNumb);
 80007ce:	687b      	ldr	r3, [r7, #4]
 80007d0:	0018      	movs	r0, r3
 80007d2:	f7ff ffaf 	bl	8000734 <SysTick_Config>
 80007d6:	0003      	movs	r3, r0
}
 80007d8:	0018      	movs	r0, r3
 80007da:	46bd      	mov	sp, r7
 80007dc:	b002      	add	sp, #8
 80007de:	bd80      	pop	{r7, pc}

080007e0 <HAL_LPTIM_Init>:
  *         LPTIM_InitTypeDef and initialize the associated handle.
  * @param  hlptim LPTIM handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
{
 80007e0:	b580      	push	{r7, lr}
 80007e2:	b084      	sub	sp, #16
 80007e4:	af00      	add	r7, sp, #0
 80007e6:	6078      	str	r0, [r7, #4]
  uint32_t tmpcfgr;

  /* Check the LPTIM handle allocation */
  if (hlptim == NULL)
 80007e8:	687b      	ldr	r3, [r7, #4]
 80007ea:	2b00      	cmp	r3, #0
 80007ec:	d101      	bne.n	80007f2 <HAL_LPTIM_Init+0x12>
  {
    return HAL_ERROR;
 80007ee:	2301      	movs	r3, #1
 80007f0:	e06c      	b.n	80008cc <HAL_LPTIM_Init+0xec>
  }
  assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
  assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
  assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));

  if (hlptim->State == HAL_LPTIM_STATE_RESET)
 80007f2:	687b      	ldr	r3, [r7, #4]
 80007f4:	222e      	movs	r2, #46	; 0x2e
 80007f6:	5c9b      	ldrb	r3, [r3, r2]
 80007f8:	b2db      	uxtb	r3, r3
 80007fa:	2b00      	cmp	r3, #0
 80007fc:	d107      	bne.n	800080e <HAL_LPTIM_Init+0x2e>
  {
    /* Allocate lock resource and initialize it */
    hlptim->Lock = HAL_UNLOCKED;
 80007fe:	687b      	ldr	r3, [r7, #4]
 8000800:	222d      	movs	r2, #45	; 0x2d
 8000802:	2100      	movs	r1, #0
 8000804:	5499      	strb	r1, [r3, r2]

    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    hlptim->MspInitCallback(hlptim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_LPTIM_MspInit(hlptim);
 8000806:	687b      	ldr	r3, [r7, #4]
 8000808:	0018      	movs	r0, r3
 800080a:	f7ff fdf1 	bl	80003f0 <HAL_LPTIM_MspInit>
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
  }

  /* Change the LPTIM state */
  hlptim->State = HAL_LPTIM_STATE_BUSY;
 800080e:	687b      	ldr	r3, [r7, #4]
 8000810:	222e      	movs	r2, #46	; 0x2e
 8000812:	2102      	movs	r1, #2
 8000814:	5499      	strb	r1, [r3, r2]

  /* Get the LPTIMx CFGR value */
  tmpcfgr = hlptim->Instance->CFGR;
 8000816:	687b      	ldr	r3, [r7, #4]
 8000818:	681b      	ldr	r3, [r3, #0]
 800081a:	68db      	ldr	r3, [r3, #12]
 800081c:	60fb      	str	r3, [r7, #12]

  if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
 800081e:	687b      	ldr	r3, [r7, #4]
 8000820:	685b      	ldr	r3, [r3, #4]
 8000822:	2b01      	cmp	r3, #1
 8000824:	d005      	beq.n	8000832 <HAL_LPTIM_Init+0x52>
 8000826:	687b      	ldr	r3, [r7, #4]
 8000828:	6a9a      	ldr	r2, [r3, #40]	; 0x28
 800082a:	2380      	movs	r3, #128	; 0x80
 800082c:	041b      	lsls	r3, r3, #16
 800082e:	429a      	cmp	r2, r3
 8000830:	d103      	bne.n	800083a <HAL_LPTIM_Init+0x5a>
  {
    tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
 8000832:	68fb      	ldr	r3, [r7, #12]
 8000834:	221e      	movs	r2, #30
 8000836:	4393      	bics	r3, r2
 8000838:	60fb      	str	r3, [r7, #12]
  }
  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
 800083a:	687b      	ldr	r3, [r7, #4]
 800083c:	695b      	ldr	r3, [r3, #20]
 800083e:	4a25      	ldr	r2, [pc, #148]	; (80008d4 <HAL_LPTIM_Init+0xf4>)
 8000840:	4293      	cmp	r3, r2
 8000842:	d003      	beq.n	800084c <HAL_LPTIM_Init+0x6c>
  {
    tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
 8000844:	68fb      	ldr	r3, [r7, #12]
 8000846:	4a24      	ldr	r2, [pc, #144]	; (80008d8 <HAL_LPTIM_Init+0xf8>)
 8000848:	4013      	ands	r3, r2
 800084a:	60fb      	str	r3, [r7, #12]
  }

  /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
  tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
 800084c:	68fb      	ldr	r3, [r7, #12]
 800084e:	4a23      	ldr	r2, [pc, #140]	; (80008dc <HAL_LPTIM_Init+0xfc>)
 8000850:	4013      	ands	r3, r2
 8000852:	60fb      	str	r3, [r7, #12]
                          LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));

  /* Set initialization parameters */
  tmpcfgr |= (hlptim->Init.Clock.Source    |
 8000854:	687b      	ldr	r3, [r7, #4]
 8000856:	685a      	ldr	r2, [r3, #4]
              hlptim->Init.Clock.Prescaler |
 8000858:	687b      	ldr	r3, [r7, #4]
 800085a:	689b      	ldr	r3, [r3, #8]
  tmpcfgr |= (hlptim->Init.Clock.Source    |
 800085c:	431a      	orrs	r2, r3
              hlptim->Init.OutputPolarity  |
 800085e:	687b      	ldr	r3, [r7, #4]
 8000860:	6a1b      	ldr	r3, [r3, #32]
              hlptim->Init.Clock.Prescaler |
 8000862:	431a      	orrs	r2, r3
              hlptim->Init.UpdateMode      |
 8000864:	687b      	ldr	r3, [r7, #4]
 8000866:	6a5b      	ldr	r3, [r3, #36]	; 0x24
              hlptim->Init.OutputPolarity  |
 8000868:	431a      	orrs	r2, r3
              hlptim->Init.CounterSource);
 800086a:	687b      	ldr	r3, [r7, #4]
 800086c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
              hlptim->Init.UpdateMode      |
 800086e:	4313      	orrs	r3, r2
  tmpcfgr |= (hlptim->Init.Clock.Source    |
 8000870:	68fa      	ldr	r2, [r7, #12]
 8000872:	4313      	orrs	r3, r2
 8000874:	60fb      	str	r3, [r7, #12]

  if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL))
 8000876:	687b      	ldr	r3, [r7, #4]
 8000878:	685b      	ldr	r3, [r3, #4]
 800087a:	2b01      	cmp	r3, #1
 800087c:	d005      	beq.n	800088a <HAL_LPTIM_Init+0xaa>
 800087e:	687b      	ldr	r3, [r7, #4]
 8000880:	6a9a      	ldr	r2, [r3, #40]	; 0x28
 8000882:	2380      	movs	r3, #128	; 0x80
 8000884:	041b      	lsls	r3, r3, #16
 8000886:	429a      	cmp	r2, r3
 8000888:	d107      	bne.n	800089a <HAL_LPTIM_Init+0xba>
  {
    tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
 800088a:	687b      	ldr	r3, [r7, #4]
 800088c:	68da      	ldr	r2, [r3, #12]
                hlptim->Init.UltraLowPowerClock.SampleTime);
 800088e:	687b      	ldr	r3, [r7, #4]
 8000890:	691b      	ldr	r3, [r3, #16]
    tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
 8000892:	4313      	orrs	r3, r2
 8000894:	68fa      	ldr	r2, [r7, #12]
 8000896:	4313      	orrs	r3, r2
 8000898:	60fb      	str	r3, [r7, #12]
  }

  if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
 800089a:	687b      	ldr	r3, [r7, #4]
 800089c:	695b      	ldr	r3, [r3, #20]
 800089e:	4a0d      	ldr	r2, [pc, #52]	; (80008d4 <HAL_LPTIM_Init+0xf4>)
 80008a0:	4293      	cmp	r3, r2
 80008a2:	d00a      	beq.n	80008ba <HAL_LPTIM_Init+0xda>
  {
    /* Enable External trigger and set the trigger source */
    tmpcfgr |= (hlptim->Init.Trigger.Source     |
 80008a4:	687b      	ldr	r3, [r7, #4]
 80008a6:	695a      	ldr	r2, [r3, #20]
                hlptim->Init.Trigger.ActiveEdge |
 80008a8:	687b      	ldr	r3, [r7, #4]
 80008aa:	699b      	ldr	r3, [r3, #24]
    tmpcfgr |= (hlptim->Init.Trigger.Source     |
 80008ac:	431a      	orrs	r2, r3
                hlptim->Init.Trigger.SampleTime);
 80008ae:	687b      	ldr	r3, [r7, #4]
 80008b0:	69db      	ldr	r3, [r3, #28]
                hlptim->Init.Trigger.ActiveEdge |
 80008b2:	4313      	orrs	r3, r2
    tmpcfgr |= (hlptim->Init.Trigger.Source     |
 80008b4:	68fa      	ldr	r2, [r7, #12]
 80008b6:	4313      	orrs	r3, r2
 80008b8:	60fb      	str	r3, [r7, #12]
  }

  /* Write to LPTIMx CFGR */
  hlptim->Instance->CFGR = tmpcfgr;
 80008ba:	687b      	ldr	r3, [r7, #4]
 80008bc:	681b      	ldr	r3, [r3, #0]
 80008be:	68fa      	ldr	r2, [r7, #12]
 80008c0:	60da      	str	r2, [r3, #12]

  /* Change the LPTIM state */
  hlptim->State = HAL_LPTIM_STATE_READY;
 80008c2:	687b      	ldr	r3, [r7, #4]
 80008c4:	222e      	movs	r2, #46	; 0x2e
 80008c6:	2101      	movs	r1, #1
 80008c8:	5499      	strb	r1, [r3, r2]

  /* Return function status */
  return HAL_OK;
 80008ca:	2300      	movs	r3, #0
}
 80008cc:	0018      	movs	r0, r3
 80008ce:	46bd      	mov	sp, r7
 80008d0:	b004      	add	sp, #16
 80008d2:	bd80      	pop	{r7, pc}
 80008d4:	0000ffff 	.word	0x0000ffff
 80008d8:	ffff1f3f 	.word	0xffff1f3f
 80008dc:	ff19f1f8 	.word	0xff19f1f8

080008e0 <HAL_LPTIM_Counter_Start_IT>:
  * @param  Period Specifies the Autoreload value.
  *         This parameter must be a value between 0x0000 and 0xFFFF.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
{
 80008e0:	b580      	push	{r7, lr}
 80008e2:	b082      	sub	sp, #8
 80008e4:	af00      	add	r7, sp, #0
 80008e6:	6078      	str	r0, [r7, #4]
 80008e8:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
  assert_param(IS_LPTIM_PERIOD(Period));

  /* Set the LPTIM state */
  hlptim->State = HAL_LPTIM_STATE_BUSY;
 80008ea:	687b      	ldr	r3, [r7, #4]
 80008ec:	222e      	movs	r2, #46	; 0x2e
 80008ee:	2102      	movs	r1, #2
 80008f0:	5499      	strb	r1, [r3, r2]

  /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
  __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
 80008f2:	4b23      	ldr	r3, [pc, #140]	; (8000980 <HAL_LPTIM_Counter_Start_IT+0xa0>)
 80008f4:	681a      	ldr	r2, [r3, #0]
 80008f6:	4b22      	ldr	r3, [pc, #136]	; (8000980 <HAL_LPTIM_Counter_Start_IT+0xa0>)
 80008f8:	2180      	movs	r1, #128	; 0x80
 80008fa:	0589      	lsls	r1, r1, #22
 80008fc:	430a      	orrs	r2, r1
 80008fe:	601a      	str	r2, [r3, #0]

  /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
  if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
 8000900:	687b      	ldr	r3, [r7, #4]
 8000902:	685b      	ldr	r3, [r3, #4]
 8000904:	2b01      	cmp	r3, #1
 8000906:	d00d      	beq.n	8000924 <HAL_LPTIM_Counter_Start_IT+0x44>
 8000908:	687b      	ldr	r3, [r7, #4]
 800090a:	6a9a      	ldr	r2, [r3, #40]	; 0x28
 800090c:	2380      	movs	r3, #128	; 0x80
 800090e:	041b      	lsls	r3, r3, #16
 8000910:	429a      	cmp	r2, r3
 8000912:	d107      	bne.n	8000924 <HAL_LPTIM_Counter_Start_IT+0x44>
  {
    /* Check if clock is prescaled */
    assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
    /* Set clock prescaler to 0 */
    hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
 8000914:	687b      	ldr	r3, [r7, #4]
 8000916:	681b      	ldr	r3, [r3, #0]
 8000918:	68da      	ldr	r2, [r3, #12]
 800091a:	687b      	ldr	r3, [r7, #4]
 800091c:	681b      	ldr	r3, [r3, #0]
 800091e:	4919      	ldr	r1, [pc, #100]	; (8000984 <HAL_LPTIM_Counter_Start_IT+0xa4>)
 8000920:	400a      	ands	r2, r1
 8000922:	60da      	str	r2, [r3, #12]
  }

  /* Enable Autoreload write complete interrupt */
  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
 8000924:	687b      	ldr	r3, [r7, #4]
 8000926:	681b      	ldr	r3, [r3, #0]
 8000928:	689a      	ldr	r2, [r3, #8]
 800092a:	687b      	ldr	r3, [r7, #4]
 800092c:	681b      	ldr	r3, [r3, #0]
 800092e:	2110      	movs	r1, #16
 8000930:	430a      	orrs	r2, r1
 8000932:	609a      	str	r2, [r3, #8]

  /* Enable Autoreload match interrupt */
  __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
 8000934:	687b      	ldr	r3, [r7, #4]
 8000936:	681b      	ldr	r3, [r3, #0]
 8000938:	689a      	ldr	r2, [r3, #8]
 800093a:	687b      	ldr	r3, [r7, #4]
 800093c:	681b      	ldr	r3, [r3, #0]
 800093e:	2102      	movs	r1, #2
 8000940:	430a      	orrs	r2, r1
 8000942:	609a      	str	r2, [r3, #8]

  /* Enable the Peripheral */
  __HAL_LPTIM_ENABLE(hlptim);
 8000944:	687b      	ldr	r3, [r7, #4]
 8000946:	681b      	ldr	r3, [r3, #0]
 8000948:	691a      	ldr	r2, [r3, #16]
 800094a:	687b      	ldr	r3, [r7, #4]
 800094c:	681b      	ldr	r3, [r3, #0]
 800094e:	2101      	movs	r1, #1
 8000950:	430a      	orrs	r2, r1
 8000952:	611a      	str	r2, [r3, #16]

  /* Load the period value in the autoreload register */
  __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
 8000954:	687b      	ldr	r3, [r7, #4]
 8000956:	681b      	ldr	r3, [r3, #0]
 8000958:	683a      	ldr	r2, [r7, #0]
 800095a:	619a      	str	r2, [r3, #24]

  /* Start timer in continuous mode */
  __HAL_LPTIM_START_CONTINUOUS(hlptim);
 800095c:	687b      	ldr	r3, [r7, #4]
 800095e:	681b      	ldr	r3, [r3, #0]
 8000960:	691a      	ldr	r2, [r3, #16]
 8000962:	687b      	ldr	r3, [r7, #4]
 8000964:	681b      	ldr	r3, [r3, #0]
 8000966:	2104      	movs	r1, #4
 8000968:	430a      	orrs	r2, r1
 800096a:	611a      	str	r2, [r3, #16]

  /* Change the TIM state*/
  hlptim->State = HAL_LPTIM_STATE_READY;
 800096c:	687b      	ldr	r3, [r7, #4]
 800096e:	222e      	movs	r2, #46	; 0x2e
 8000970:	2101      	movs	r1, #1
 8000972:	5499      	strb	r1, [r3, r2]

  /* Return function status */
  return HAL_OK;
 8000974:	2300      	movs	r3, #0
}
 8000976:	0018      	movs	r0, r3
 8000978:	46bd      	mov	sp, r7
 800097a:	b002      	add	sp, #8
 800097c:	bd80      	pop	{r7, pc}
 800097e:	46c0      	nop			; (mov r8, r8)
 8000980:	40010400 	.word	0x40010400
 8000984:	fffff1ff 	.word	0xfffff1ff

08000988 <HAL_LPTIM_IRQHandler>:
  * @brief  Handle LPTIM interrupt request.
  * @param  hlptim LPTIM handle
  * @retval None
  */
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
{
 8000988:	b580      	push	{r7, lr}
 800098a:	b082      	sub	sp, #8
 800098c:	af00      	add	r7, sp, #0
 800098e:	6078      	str	r0, [r7, #4]
  /* Compare match interrupt */
  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
 8000990:	687b      	ldr	r3, [r7, #4]
 8000992:	681b      	ldr	r3, [r3, #0]
 8000994:	681b      	ldr	r3, [r3, #0]
 8000996:	2201      	movs	r2, #1
 8000998:	4013      	ands	r3, r2
 800099a:	2b01      	cmp	r3, #1
 800099c:	d10e      	bne.n	80009bc <HAL_LPTIM_IRQHandler+0x34>
  {
    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
 800099e:	687b      	ldr	r3, [r7, #4]
 80009a0:	681b      	ldr	r3, [r3, #0]
 80009a2:	689b      	ldr	r3, [r3, #8]
 80009a4:	2201      	movs	r2, #1
 80009a6:	4013      	ands	r3, r2
 80009a8:	2b01      	cmp	r3, #1
 80009aa:	d107      	bne.n	80009bc <HAL_LPTIM_IRQHandler+0x34>
    {
      /* Clear Compare match flag */
      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
 80009ac:	687b      	ldr	r3, [r7, #4]
 80009ae:	681b      	ldr	r3, [r3, #0]
 80009b0:	2201      	movs	r2, #1
 80009b2:	605a      	str	r2, [r3, #4]

      /* Compare match Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
      hlptim->CompareMatchCallback(hlptim);
#else
      HAL_LPTIM_CompareMatchCallback(hlptim);
 80009b4:	687b      	ldr	r3, [r7, #4]
 80009b6:	0018      	movs	r0, r3
 80009b8:	f000 f888 	bl	8000acc <HAL_LPTIM_CompareMatchCallback>
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
    }
  }

  /* Autoreload match interrupt */
  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
 80009bc:	687b      	ldr	r3, [r7, #4]
 80009be:	681b      	ldr	r3, [r3, #0]
 80009c0:	681b      	ldr	r3, [r3, #0]
 80009c2:	2202      	movs	r2, #2
 80009c4:	4013      	ands	r3, r2
 80009c6:	2b02      	cmp	r3, #2
 80009c8:	d10e      	bne.n	80009e8 <HAL_LPTIM_IRQHandler+0x60>
  {
    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
 80009ca:	687b      	ldr	r3, [r7, #4]
 80009cc:	681b      	ldr	r3, [r3, #0]
 80009ce:	689b      	ldr	r3, [r3, #8]
 80009d0:	2202      	movs	r2, #2
 80009d2:	4013      	ands	r3, r2
 80009d4:	2b02      	cmp	r3, #2
 80009d6:	d107      	bne.n	80009e8 <HAL_LPTIM_IRQHandler+0x60>
    {
      /* Clear Autoreload match flag */
      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
 80009d8:	687b      	ldr	r3, [r7, #4]
 80009da:	681b      	ldr	r3, [r3, #0]
 80009dc:	2202      	movs	r2, #2
 80009de:	605a      	str	r2, [r3, #4]

      /* Autoreload match Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
      hlptim->AutoReloadMatchCallback(hlptim);
#else
      HAL_LPTIM_AutoReloadMatchCallback(hlptim);
 80009e0:	687b      	ldr	r3, [r7, #4]
 80009e2:	0018      	movs	r0, r3
 80009e4:	f000 f87a 	bl	8000adc <HAL_LPTIM_AutoReloadMatchCallback>
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
    }
  }

  /* Trigger detected interrupt */
  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
 80009e8:	687b      	ldr	r3, [r7, #4]
 80009ea:	681b      	ldr	r3, [r3, #0]
 80009ec:	681b      	ldr	r3, [r3, #0]
 80009ee:	2204      	movs	r2, #4
 80009f0:	4013      	ands	r3, r2
 80009f2:	2b04      	cmp	r3, #4
 80009f4:	d10e      	bne.n	8000a14 <HAL_LPTIM_IRQHandler+0x8c>
  {
    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
 80009f6:	687b      	ldr	r3, [r7, #4]
 80009f8:	681b      	ldr	r3, [r3, #0]
 80009fa:	689b      	ldr	r3, [r3, #8]
 80009fc:	2204      	movs	r2, #4
 80009fe:	4013      	ands	r3, r2
 8000a00:	2b04      	cmp	r3, #4
 8000a02:	d107      	bne.n	8000a14 <HAL_LPTIM_IRQHandler+0x8c>
    {
      /* Clear Trigger detected flag */
      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
 8000a04:	687b      	ldr	r3, [r7, #4]
 8000a06:	681b      	ldr	r3, [r3, #0]
 8000a08:	2204      	movs	r2, #4
 8000a0a:	605a      	str	r2, [r3, #4]

      /* Trigger detected callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
      hlptim->TriggerCallback(hlptim);
#else
      HAL_LPTIM_TriggerCallback(hlptim);
 8000a0c:	687b      	ldr	r3, [r7, #4]
 8000a0e:	0018      	movs	r0, r3
 8000a10:	f000 f86c 	bl	8000aec <HAL_LPTIM_TriggerCallback>
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
    }
  }

  /* Compare write interrupt */
  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
 8000a14:	687b      	ldr	r3, [r7, #4]
 8000a16:	681b      	ldr	r3, [r3, #0]
 8000a18:	681b      	ldr	r3, [r3, #0]
 8000a1a:	2208      	movs	r2, #8
 8000a1c:	4013      	ands	r3, r2
 8000a1e:	2b08      	cmp	r3, #8
 8000a20:	d10e      	bne.n	8000a40 <HAL_LPTIM_IRQHandler+0xb8>
  {
    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
 8000a22:	687b      	ldr	r3, [r7, #4]
 8000a24:	681b      	ldr	r3, [r3, #0]
 8000a26:	689b      	ldr	r3, [r3, #8]
 8000a28:	2208      	movs	r2, #8
 8000a2a:	4013      	ands	r3, r2
 8000a2c:	2b08      	cmp	r3, #8
 8000a2e:	d107      	bne.n	8000a40 <HAL_LPTIM_IRQHandler+0xb8>
    {
      /* Clear Compare write flag */
      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
 8000a30:	687b      	ldr	r3, [r7, #4]
 8000a32:	681b      	ldr	r3, [r3, #0]
 8000a34:	2208      	movs	r2, #8
 8000a36:	605a      	str	r2, [r3, #4]

      /* Compare write Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
      hlptim->CompareWriteCallback(hlptim);
#else
      HAL_LPTIM_CompareWriteCallback(hlptim);
 8000a38:	687b      	ldr	r3, [r7, #4]
 8000a3a:	0018      	movs	r0, r3
 8000a3c:	f000 f85e 	bl	8000afc <HAL_LPTIM_CompareWriteCallback>
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
    }
  }

  /* Autoreload write interrupt */
  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
 8000a40:	687b      	ldr	r3, [r7, #4]
 8000a42:	681b      	ldr	r3, [r3, #0]
 8000a44:	681b      	ldr	r3, [r3, #0]
 8000a46:	2210      	movs	r2, #16
 8000a48:	4013      	ands	r3, r2
 8000a4a:	2b10      	cmp	r3, #16
 8000a4c:	d10e      	bne.n	8000a6c <HAL_LPTIM_IRQHandler+0xe4>
  {
    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
 8000a4e:	687b      	ldr	r3, [r7, #4]
 8000a50:	681b      	ldr	r3, [r3, #0]
 8000a52:	689b      	ldr	r3, [r3, #8]
 8000a54:	2210      	movs	r2, #16
 8000a56:	4013      	ands	r3, r2
 8000a58:	2b10      	cmp	r3, #16
 8000a5a:	d107      	bne.n	8000a6c <HAL_LPTIM_IRQHandler+0xe4>
    {
      /* Clear Autoreload write flag */
      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
 8000a5c:	687b      	ldr	r3, [r7, #4]
 8000a5e:	681b      	ldr	r3, [r3, #0]
 8000a60:	2210      	movs	r2, #16
 8000a62:	605a      	str	r2, [r3, #4]

      /* Autoreload write Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
      hlptim->AutoReloadWriteCallback(hlptim);
#else
      HAL_LPTIM_AutoReloadWriteCallback(hlptim);
 8000a64:	687b      	ldr	r3, [r7, #4]
 8000a66:	0018      	movs	r0, r3
 8000a68:	f000 f850 	bl	8000b0c <HAL_LPTIM_AutoReloadWriteCallback>
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
    }
  }

  /* Direction counter changed from Down to Up interrupt */
  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
 8000a6c:	687b      	ldr	r3, [r7, #4]
 8000a6e:	681b      	ldr	r3, [r3, #0]
 8000a70:	681b      	ldr	r3, [r3, #0]
 8000a72:	2220      	movs	r2, #32
 8000a74:	4013      	ands	r3, r2
 8000a76:	2b20      	cmp	r3, #32
 8000a78:	d10e      	bne.n	8000a98 <HAL_LPTIM_IRQHandler+0x110>
  {
    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
 8000a7a:	687b      	ldr	r3, [r7, #4]
 8000a7c:	681b      	ldr	r3, [r3, #0]
 8000a7e:	689b      	ldr	r3, [r3, #8]
 8000a80:	2220      	movs	r2, #32
 8000a82:	4013      	ands	r3, r2
 8000a84:	2b20      	cmp	r3, #32
 8000a86:	d107      	bne.n	8000a98 <HAL_LPTIM_IRQHandler+0x110>
    {
      /* Clear Direction counter changed from Down to Up flag */
      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
 8000a88:	687b      	ldr	r3, [r7, #4]
 8000a8a:	681b      	ldr	r3, [r3, #0]
 8000a8c:	2220      	movs	r2, #32
 8000a8e:	605a      	str	r2, [r3, #4]

      /* Direction counter changed from Down to Up Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
      hlptim->DirectionUpCallback(hlptim);
#else
      HAL_LPTIM_DirectionUpCallback(hlptim);
 8000a90:	687b      	ldr	r3, [r7, #4]
 8000a92:	0018      	movs	r0, r3
 8000a94:	f000 f842 	bl	8000b1c <HAL_LPTIM_DirectionUpCallback>
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
    }
  }

  /* Direction counter changed from Up to Down interrupt */
  if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
 8000a98:	687b      	ldr	r3, [r7, #4]
 8000a9a:	681b      	ldr	r3, [r3, #0]
 8000a9c:	681b      	ldr	r3, [r3, #0]
 8000a9e:	2240      	movs	r2, #64	; 0x40
 8000aa0:	4013      	ands	r3, r2
 8000aa2:	2b40      	cmp	r3, #64	; 0x40
 8000aa4:	d10e      	bne.n	8000ac4 <HAL_LPTIM_IRQHandler+0x13c>
  {
    if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
 8000aa6:	687b      	ldr	r3, [r7, #4]
 8000aa8:	681b      	ldr	r3, [r3, #0]
 8000aaa:	689b      	ldr	r3, [r3, #8]
 8000aac:	2240      	movs	r2, #64	; 0x40
 8000aae:	4013      	ands	r3, r2
 8000ab0:	2b40      	cmp	r3, #64	; 0x40
 8000ab2:	d107      	bne.n	8000ac4 <HAL_LPTIM_IRQHandler+0x13c>
    {
      /* Clear Direction counter changed from Up to Down flag */
      __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
 8000ab4:	687b      	ldr	r3, [r7, #4]
 8000ab6:	681b      	ldr	r3, [r3, #0]
 8000ab8:	2240      	movs	r2, #64	; 0x40
 8000aba:	605a      	str	r2, [r3, #4]

      /* Direction counter changed from Up to Down Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
      hlptim->DirectionDownCallback(hlptim);
#else
      HAL_LPTIM_DirectionDownCallback(hlptim);
 8000abc:	687b      	ldr	r3, [r7, #4]
 8000abe:	0018      	movs	r0, r3
 8000ac0:	f000 f834 	bl	8000b2c <HAL_LPTIM_DirectionDownCallback>
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
    }
  }
}
 8000ac4:	46c0      	nop			; (mov r8, r8)
 8000ac6:	46bd      	mov	sp, r7
 8000ac8:	b002      	add	sp, #8
 8000aca:	bd80      	pop	{r7, pc}

08000acc <HAL_LPTIM_CompareMatchCallback>:
  * @brief  Compare match callback in non-blocking mode.
  * @param  hlptim LPTIM handle
  * @retval None
  */
__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
 8000acc:	b580      	push	{r7, lr}
 8000ace:	b082      	sub	sp, #8
 8000ad0:	af00      	add	r7, sp, #0
 8000ad2:	6078      	str	r0, [r7, #4]
  UNUSED(hlptim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
   */
}
 8000ad4:	46c0      	nop			; (mov r8, r8)
 8000ad6:	46bd      	mov	sp, r7
 8000ad8:	b002      	add	sp, #8
 8000ada:	bd80      	pop	{r7, pc}

08000adc <HAL_LPTIM_AutoReloadMatchCallback>:
  * @brief  Autoreload match callback in non-blocking mode.
  * @param  hlptim LPTIM handle
  * @retval None
  */
__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
 8000adc:	b580      	push	{r7, lr}
 8000ade:	b082      	sub	sp, #8
 8000ae0:	af00      	add	r7, sp, #0
 8000ae2:	6078      	str	r0, [r7, #4]
  UNUSED(hlptim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
   */
}
 8000ae4:	46c0      	nop			; (mov r8, r8)
 8000ae6:	46bd      	mov	sp, r7
 8000ae8:	b002      	add	sp, #8
 8000aea:	bd80      	pop	{r7, pc}

08000aec <HAL_LPTIM_TriggerCallback>:
  * @brief  Trigger detected callback in non-blocking mode.
  * @param  hlptim LPTIM handle
  * @retval None
  */
__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
{
 8000aec:	b580      	push	{r7, lr}
 8000aee:	b082      	sub	sp, #8
 8000af0:	af00      	add	r7, sp, #0
 8000af2:	6078      	str	r0, [r7, #4]
  UNUSED(hlptim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_LPTIM_TriggerCallback could be implemented in the user file
   */
}
 8000af4:	46c0      	nop			; (mov r8, r8)
 8000af6:	46bd      	mov	sp, r7
 8000af8:	b002      	add	sp, #8
 8000afa:	bd80      	pop	{r7, pc}

08000afc <HAL_LPTIM_CompareWriteCallback>:
  * @brief  Compare write callback in non-blocking mode.
  * @param  hlptim LPTIM handle
  * @retval None
  */
__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
 8000afc:	b580      	push	{r7, lr}
 8000afe:	b082      	sub	sp, #8
 8000b00:	af00      	add	r7, sp, #0
 8000b02:	6078      	str	r0, [r7, #4]
  UNUSED(hlptim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
   */
}
 8000b04:	46c0      	nop			; (mov r8, r8)
 8000b06:	46bd      	mov	sp, r7
 8000b08:	b002      	add	sp, #8
 8000b0a:	bd80      	pop	{r7, pc}

08000b0c <HAL_LPTIM_AutoReloadWriteCallback>:
  * @brief  Autoreload write callback in non-blocking mode.
  * @param  hlptim LPTIM handle
  * @retval None
  */
__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
 8000b0c:	b580      	push	{r7, lr}
 8000b0e:	b082      	sub	sp, #8
 8000b10:	af00      	add	r7, sp, #0
 8000b12:	6078      	str	r0, [r7, #4]
  UNUSED(hlptim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
   */
}
 8000b14:	46c0      	nop			; (mov r8, r8)
 8000b16:	46bd      	mov	sp, r7
 8000b18:	b002      	add	sp, #8
 8000b1a:	bd80      	pop	{r7, pc}

08000b1c <HAL_LPTIM_DirectionUpCallback>:
  * @brief  Direction counter changed from Down to Up callback in non-blocking mode.
  * @param  hlptim LPTIM handle
  * @retval None
  */
__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
{
 8000b1c:	b580      	push	{r7, lr}
 8000b1e:	b082      	sub	sp, #8
 8000b20:	af00      	add	r7, sp, #0
 8000b22:	6078      	str	r0, [r7, #4]
  UNUSED(hlptim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
   */
}
 8000b24:	46c0      	nop			; (mov r8, r8)
 8000b26:	46bd      	mov	sp, r7
 8000b28:	b002      	add	sp, #8
 8000b2a:	bd80      	pop	{r7, pc}

08000b2c <HAL_LPTIM_DirectionDownCallback>:
  * @brief  Direction counter changed from Up to Down callback in non-blocking mode.
  * @param  hlptim LPTIM handle
  * @retval None
  */
__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
{
 8000b2c:	b580      	push	{r7, lr}
 8000b2e:	b082      	sub	sp, #8
 8000b30:	af00      	add	r7, sp, #0
 8000b32:	6078      	str	r0, [r7, #4]
  UNUSED(hlptim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
   */
}
 8000b34:	46c0      	nop			; (mov r8, r8)
 8000b36:	46bd      	mov	sp, r7
 8000b38:	b002      	add	sp, #8
 8000b3a:	bd80      	pop	{r7, pc}

08000b3c <HAL_PWR_EnableBkUpAccess>:
  * @note   If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
  *         Backup Domain Access should be kept enabled.
  * @retval None
  */
void HAL_PWR_EnableBkUpAccess(void)
{
 8000b3c:	b580      	push	{r7, lr}
 8000b3e:	af00      	add	r7, sp, #0
  /* Enable access to RTC and backup registers */
  SET_BIT(PWR->CR, PWR_CR_DBP);
 8000b40:	4b04      	ldr	r3, [pc, #16]	; (8000b54 <HAL_PWR_EnableBkUpAccess+0x18>)
 8000b42:	681a      	ldr	r2, [r3, #0]
 8000b44:	4b03      	ldr	r3, [pc, #12]	; (8000b54 <HAL_PWR_EnableBkUpAccess+0x18>)
 8000b46:	2180      	movs	r1, #128	; 0x80
 8000b48:	0049      	lsls	r1, r1, #1
 8000b4a:	430a      	orrs	r2, r1
 8000b4c:	601a      	str	r2, [r3, #0]
}
 8000b4e:	46c0      	nop			; (mov r8, r8)
 8000b50:	46bd      	mov	sp, r7
 8000b52:	bd80      	pop	{r7, pc}
 8000b54:	40007000 	.word	0x40007000

08000b58 <HAL_RCC_OscConfig>:
  *         supported by this macro. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8000b58:	b5b0      	push	{r4, r5, r7, lr}
 8000b5a:	b08a      	sub	sp, #40	; 0x28
 8000b5c:	af00      	add	r7, sp, #0
 8000b5e:	6078      	str	r0, [r7, #4]
  uint32_t hsi_state;
  HAL_StatusTypeDef status;
  uint32_t sysclk_source, pll_config;

  /* Check the parameters */
  if(RCC_OscInitStruct == NULL)
 8000b60:	687b      	ldr	r3, [r7, #4]
 8000b62:	2b00      	cmp	r3, #0
 8000b64:	d102      	bne.n	8000b6c <HAL_RCC_OscConfig+0x14>
  {
    return HAL_ERROR;
 8000b66:	2301      	movs	r3, #1
 8000b68:	f000 fbbc 	bl	80012e4 <HAL_RCC_OscConfig+0x78c>
  }

  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
 8000b6c:	4bc8      	ldr	r3, [pc, #800]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000b6e:	68db      	ldr	r3, [r3, #12]
 8000b70:	220c      	movs	r2, #12
 8000b72:	4013      	ands	r3, r2
 8000b74:	61fb      	str	r3, [r7, #28]
  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
 8000b76:	4bc6      	ldr	r3, [pc, #792]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000b78:	68da      	ldr	r2, [r3, #12]
 8000b7a:	2380      	movs	r3, #128	; 0x80
 8000b7c:	025b      	lsls	r3, r3, #9
 8000b7e:	4013      	ands	r3, r2
 8000b80:	61bb      	str	r3, [r7, #24]

  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000b82:	687b      	ldr	r3, [r7, #4]
 8000b84:	681b      	ldr	r3, [r3, #0]
 8000b86:	2201      	movs	r2, #1
 8000b88:	4013      	ands	r3, r2
 8000b8a:	d100      	bne.n	8000b8e <HAL_RCC_OscConfig+0x36>
 8000b8c:	e07e      	b.n	8000c8c <HAL_RCC_OscConfig+0x134>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
 8000b8e:	69fb      	ldr	r3, [r7, #28]
 8000b90:	2b08      	cmp	r3, #8
 8000b92:	d007      	beq.n	8000ba4 <HAL_RCC_OscConfig+0x4c>
       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
 8000b94:	69fb      	ldr	r3, [r7, #28]
 8000b96:	2b0c      	cmp	r3, #12
 8000b98:	d112      	bne.n	8000bc0 <HAL_RCC_OscConfig+0x68>
 8000b9a:	69ba      	ldr	r2, [r7, #24]
 8000b9c:	2380      	movs	r3, #128	; 0x80
 8000b9e:	025b      	lsls	r3, r3, #9
 8000ba0:	429a      	cmp	r2, r3
 8000ba2:	d10d      	bne.n	8000bc0 <HAL_RCC_OscConfig+0x68>
    {
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8000ba4:	4bba      	ldr	r3, [pc, #744]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000ba6:	681a      	ldr	r2, [r3, #0]
 8000ba8:	2380      	movs	r3, #128	; 0x80
 8000baa:	029b      	lsls	r3, r3, #10
 8000bac:	4013      	ands	r3, r2
 8000bae:	d100      	bne.n	8000bb2 <HAL_RCC_OscConfig+0x5a>
 8000bb0:	e06b      	b.n	8000c8a <HAL_RCC_OscConfig+0x132>
 8000bb2:	687b      	ldr	r3, [r7, #4]
 8000bb4:	685b      	ldr	r3, [r3, #4]
 8000bb6:	2b00      	cmp	r3, #0
 8000bb8:	d167      	bne.n	8000c8a <HAL_RCC_OscConfig+0x132>
      {
        return HAL_ERROR;
 8000bba:	2301      	movs	r3, #1
 8000bbc:	f000 fb92 	bl	80012e4 <HAL_RCC_OscConfig+0x78c>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8000bc0:	687b      	ldr	r3, [r7, #4]
 8000bc2:	685a      	ldr	r2, [r3, #4]
 8000bc4:	2380      	movs	r3, #128	; 0x80
 8000bc6:	025b      	lsls	r3, r3, #9
 8000bc8:	429a      	cmp	r2, r3
 8000bca:	d107      	bne.n	8000bdc <HAL_RCC_OscConfig+0x84>
 8000bcc:	4bb0      	ldr	r3, [pc, #704]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000bce:	681a      	ldr	r2, [r3, #0]
 8000bd0:	4baf      	ldr	r3, [pc, #700]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000bd2:	2180      	movs	r1, #128	; 0x80
 8000bd4:	0249      	lsls	r1, r1, #9
 8000bd6:	430a      	orrs	r2, r1
 8000bd8:	601a      	str	r2, [r3, #0]
 8000bda:	e027      	b.n	8000c2c <HAL_RCC_OscConfig+0xd4>
 8000bdc:	687b      	ldr	r3, [r7, #4]
 8000bde:	685a      	ldr	r2, [r3, #4]
 8000be0:	23a0      	movs	r3, #160	; 0xa0
 8000be2:	02db      	lsls	r3, r3, #11
 8000be4:	429a      	cmp	r2, r3
 8000be6:	d10e      	bne.n	8000c06 <HAL_RCC_OscConfig+0xae>
 8000be8:	4ba9      	ldr	r3, [pc, #676]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000bea:	681a      	ldr	r2, [r3, #0]
 8000bec:	4ba8      	ldr	r3, [pc, #672]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000bee:	2180      	movs	r1, #128	; 0x80
 8000bf0:	02c9      	lsls	r1, r1, #11
 8000bf2:	430a      	orrs	r2, r1
 8000bf4:	601a      	str	r2, [r3, #0]
 8000bf6:	4ba6      	ldr	r3, [pc, #664]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000bf8:	681a      	ldr	r2, [r3, #0]
 8000bfa:	4ba5      	ldr	r3, [pc, #660]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000bfc:	2180      	movs	r1, #128	; 0x80
 8000bfe:	0249      	lsls	r1, r1, #9
 8000c00:	430a      	orrs	r2, r1
 8000c02:	601a      	str	r2, [r3, #0]
 8000c04:	e012      	b.n	8000c2c <HAL_RCC_OscConfig+0xd4>
 8000c06:	4ba2      	ldr	r3, [pc, #648]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000c08:	681a      	ldr	r2, [r3, #0]
 8000c0a:	4ba1      	ldr	r3, [pc, #644]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000c0c:	49a1      	ldr	r1, [pc, #644]	; (8000e94 <HAL_RCC_OscConfig+0x33c>)
 8000c0e:	400a      	ands	r2, r1
 8000c10:	601a      	str	r2, [r3, #0]
 8000c12:	4b9f      	ldr	r3, [pc, #636]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000c14:	681a      	ldr	r2, [r3, #0]
 8000c16:	2380      	movs	r3, #128	; 0x80
 8000c18:	025b      	lsls	r3, r3, #9
 8000c1a:	4013      	ands	r3, r2
 8000c1c:	60fb      	str	r3, [r7, #12]
 8000c1e:	68fb      	ldr	r3, [r7, #12]
 8000c20:	4b9b      	ldr	r3, [pc, #620]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000c22:	681a      	ldr	r2, [r3, #0]
 8000c24:	4b9a      	ldr	r3, [pc, #616]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000c26:	499c      	ldr	r1, [pc, #624]	; (8000e98 <HAL_RCC_OscConfig+0x340>)
 8000c28:	400a      	ands	r2, r1
 8000c2a:	601a      	str	r2, [r3, #0]

      /* Check the HSE State */
      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 8000c2c:	687b      	ldr	r3, [r7, #4]
 8000c2e:	685b      	ldr	r3, [r3, #4]
 8000c30:	2b00      	cmp	r3, #0
 8000c32:	d015      	beq.n	8000c60 <HAL_RCC_OscConfig+0x108>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000c34:	f7ff fcf0 	bl	8000618 <HAL_GetTick>
 8000c38:	0003      	movs	r3, r0
 8000c3a:	617b      	str	r3, [r7, #20]

        /* Wait till HSE is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 8000c3c:	e009      	b.n	8000c52 <HAL_RCC_OscConfig+0xfa>
        {
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000c3e:	f7ff fceb 	bl	8000618 <HAL_GetTick>
 8000c42:	0002      	movs	r2, r0
 8000c44:	697b      	ldr	r3, [r7, #20]
 8000c46:	1ad3      	subs	r3, r2, r3
 8000c48:	2b64      	cmp	r3, #100	; 0x64
 8000c4a:	d902      	bls.n	8000c52 <HAL_RCC_OscConfig+0xfa>
          {
            return HAL_TIMEOUT;
 8000c4c:	2303      	movs	r3, #3
 8000c4e:	f000 fb49 	bl	80012e4 <HAL_RCC_OscConfig+0x78c>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 8000c52:	4b8f      	ldr	r3, [pc, #572]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000c54:	681a      	ldr	r2, [r3, #0]
 8000c56:	2380      	movs	r3, #128	; 0x80
 8000c58:	029b      	lsls	r3, r3, #10
 8000c5a:	4013      	ands	r3, r2
 8000c5c:	d0ef      	beq.n	8000c3e <HAL_RCC_OscConfig+0xe6>
 8000c5e:	e015      	b.n	8000c8c <HAL_RCC_OscConfig+0x134>
        }
      }
      else
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000c60:	f7ff fcda 	bl	8000618 <HAL_GetTick>
 8000c64:	0003      	movs	r3, r0
 8000c66:	617b      	str	r3, [r7, #20]

        /* Wait till HSE is disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
 8000c68:	e008      	b.n	8000c7c <HAL_RCC_OscConfig+0x124>
        {
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000c6a:	f7ff fcd5 	bl	8000618 <HAL_GetTick>
 8000c6e:	0002      	movs	r2, r0
 8000c70:	697b      	ldr	r3, [r7, #20]
 8000c72:	1ad3      	subs	r3, r2, r3
 8000c74:	2b64      	cmp	r3, #100	; 0x64
 8000c76:	d901      	bls.n	8000c7c <HAL_RCC_OscConfig+0x124>
          {
            return HAL_TIMEOUT;
 8000c78:	2303      	movs	r3, #3
 8000c7a:	e333      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
 8000c7c:	4b84      	ldr	r3, [pc, #528]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000c7e:	681a      	ldr	r2, [r3, #0]
 8000c80:	2380      	movs	r3, #128	; 0x80
 8000c82:	029b      	lsls	r3, r3, #10
 8000c84:	4013      	ands	r3, r2
 8000c86:	d1f0      	bne.n	8000c6a <HAL_RCC_OscConfig+0x112>
 8000c88:	e000      	b.n	8000c8c <HAL_RCC_OscConfig+0x134>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8000c8a:	46c0      	nop			; (mov r8, r8)
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8000c8c:	687b      	ldr	r3, [r7, #4]
 8000c8e:	681b      	ldr	r3, [r3, #0]
 8000c90:	2202      	movs	r2, #2
 8000c92:	4013      	ands	r3, r2
 8000c94:	d100      	bne.n	8000c98 <HAL_RCC_OscConfig+0x140>
 8000c96:	e098      	b.n	8000dca <HAL_RCC_OscConfig+0x272>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    hsi_state = RCC_OscInitStruct->HSIState;
 8000c98:	687b      	ldr	r3, [r7, #4]
 8000c9a:	68db      	ldr	r3, [r3, #12]
 8000c9c:	627b      	str	r3, [r7, #36]	; 0x24

#if defined(RCC_CR_HSIOUTEN)
    if((hsi_state & RCC_HSI_OUTEN) != 0U)
 8000c9e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8000ca0:	2220      	movs	r2, #32
 8000ca2:	4013      	ands	r3, r2
 8000ca4:	d009      	beq.n	8000cba <HAL_RCC_OscConfig+0x162>
    {
      /* HSI Output enable for timer requested */
      SET_BIT(RCC->CR, RCC_CR_HSIOUTEN);
 8000ca6:	4b7a      	ldr	r3, [pc, #488]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000ca8:	681a      	ldr	r2, [r3, #0]
 8000caa:	4b79      	ldr	r3, [pc, #484]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000cac:	2120      	movs	r1, #32
 8000cae:	430a      	orrs	r2, r1
 8000cb0:	601a      	str	r2, [r3, #0]

      hsi_state &= ~RCC_CR_HSIOUTEN;
 8000cb2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8000cb4:	2220      	movs	r2, #32
 8000cb6:	4393      	bics	r3, r2
 8000cb8:	627b      	str	r3, [r7, #36]	; 0x24
    }
#endif

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
 8000cba:	69fb      	ldr	r3, [r7, #28]
 8000cbc:	2b04      	cmp	r3, #4
 8000cbe:	d005      	beq.n	8000ccc <HAL_RCC_OscConfig+0x174>
       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
 8000cc0:	69fb      	ldr	r3, [r7, #28]
 8000cc2:	2b0c      	cmp	r3, #12
 8000cc4:	d13d      	bne.n	8000d42 <HAL_RCC_OscConfig+0x1ea>
 8000cc6:	69bb      	ldr	r3, [r7, #24]
 8000cc8:	2b00      	cmp	r3, #0
 8000cca:	d13a      	bne.n	8000d42 <HAL_RCC_OscConfig+0x1ea>
    {
      /* When HSI is used as system clock it will not disabled */
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (hsi_state == RCC_HSI_OFF))
 8000ccc:	4b70      	ldr	r3, [pc, #448]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000cce:	681b      	ldr	r3, [r3, #0]
 8000cd0:	2204      	movs	r2, #4
 8000cd2:	4013      	ands	r3, r2
 8000cd4:	d004      	beq.n	8000ce0 <HAL_RCC_OscConfig+0x188>
 8000cd6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8000cd8:	2b00      	cmp	r3, #0
 8000cda:	d101      	bne.n	8000ce0 <HAL_RCC_OscConfig+0x188>
      {
        return HAL_ERROR;
 8000cdc:	2301      	movs	r3, #1
 8000cde:	e301      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
      }
      /* Otherwise, just the calibration and HSI or HSIdiv4 are allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8000ce0:	4b6b      	ldr	r3, [pc, #428]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000ce2:	685b      	ldr	r3, [r3, #4]
 8000ce4:	4a6d      	ldr	r2, [pc, #436]	; (8000e9c <HAL_RCC_OscConfig+0x344>)
 8000ce6:	4013      	ands	r3, r2
 8000ce8:	0019      	movs	r1, r3
 8000cea:	687b      	ldr	r3, [r7, #4]
 8000cec:	691b      	ldr	r3, [r3, #16]
 8000cee:	021a      	lsls	r2, r3, #8
 8000cf0:	4b67      	ldr	r3, [pc, #412]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000cf2:	430a      	orrs	r2, r1
 8000cf4:	605a      	str	r2, [r3, #4]

        /* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
        __HAL_RCC_HSI_CONFIG(hsi_state);
 8000cf6:	4b66      	ldr	r3, [pc, #408]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000cf8:	681b      	ldr	r3, [r3, #0]
 8000cfa:	2209      	movs	r2, #9
 8000cfc:	4393      	bics	r3, r2
 8000cfe:	0019      	movs	r1, r3
 8000d00:	4b63      	ldr	r3, [pc, #396]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000d02:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 8000d04:	430a      	orrs	r2, r1
 8000d06:	601a      	str	r2, [r3, #0]
      }

      /* Update the SystemCoreClock global variable */
      SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 8000d08:	f000 fc20 	bl	800154c <HAL_RCC_GetSysClockFreq>
 8000d0c:	0001      	movs	r1, r0
 8000d0e:	4b60      	ldr	r3, [pc, #384]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000d10:	68db      	ldr	r3, [r3, #12]
 8000d12:	091b      	lsrs	r3, r3, #4
 8000d14:	220f      	movs	r2, #15
 8000d16:	4013      	ands	r3, r2
 8000d18:	4a61      	ldr	r2, [pc, #388]	; (8000ea0 <HAL_RCC_OscConfig+0x348>)
 8000d1a:	5cd3      	ldrb	r3, [r2, r3]
 8000d1c:	000a      	movs	r2, r1
 8000d1e:	40da      	lsrs	r2, r3
 8000d20:	4b60      	ldr	r3, [pc, #384]	; (8000ea4 <HAL_RCC_OscConfig+0x34c>)
 8000d22:	601a      	str	r2, [r3, #0]

      /* Configure the source of time base considering new system clocks settings*/
      status = HAL_InitTick (TICK_INT_PRIORITY);
 8000d24:	2513      	movs	r5, #19
 8000d26:	197c      	adds	r4, r7, r5
 8000d28:	2000      	movs	r0, #0
 8000d2a:	f7ff fc2f 	bl	800058c <HAL_InitTick>
 8000d2e:	0003      	movs	r3, r0
 8000d30:	7023      	strb	r3, [r4, #0]
      if(status != HAL_OK)
 8000d32:	197b      	adds	r3, r7, r5
 8000d34:	781b      	ldrb	r3, [r3, #0]
 8000d36:	2b00      	cmp	r3, #0
 8000d38:	d047      	beq.n	8000dca <HAL_RCC_OscConfig+0x272>
      {
        return status;
 8000d3a:	2313      	movs	r3, #19
 8000d3c:	18fb      	adds	r3, r7, r3
 8000d3e:	781b      	ldrb	r3, [r3, #0]
 8000d40:	e2d0      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
      }
    }
    else
    {
      /* Check the HSI State */
      if(hsi_state != RCC_HSI_OFF)
 8000d42:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8000d44:	2b00      	cmp	r3, #0
 8000d46:	d027      	beq.n	8000d98 <HAL_RCC_OscConfig+0x240>
      {
        /* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
        __HAL_RCC_HSI_CONFIG(hsi_state);
 8000d48:	4b51      	ldr	r3, [pc, #324]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000d4a:	681b      	ldr	r3, [r3, #0]
 8000d4c:	2209      	movs	r2, #9
 8000d4e:	4393      	bics	r3, r2
 8000d50:	0019      	movs	r1, r3
 8000d52:	4b4f      	ldr	r3, [pc, #316]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000d54:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 8000d56:	430a      	orrs	r2, r1
 8000d58:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000d5a:	f7ff fc5d 	bl	8000618 <HAL_GetTick>
 8000d5e:	0003      	movs	r3, r0
 8000d60:	617b      	str	r3, [r7, #20]

        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 8000d62:	e008      	b.n	8000d76 <HAL_RCC_OscConfig+0x21e>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000d64:	f7ff fc58 	bl	8000618 <HAL_GetTick>
 8000d68:	0002      	movs	r2, r0
 8000d6a:	697b      	ldr	r3, [r7, #20]
 8000d6c:	1ad3      	subs	r3, r2, r3
 8000d6e:	2b02      	cmp	r3, #2
 8000d70:	d901      	bls.n	8000d76 <HAL_RCC_OscConfig+0x21e>
          {
            return HAL_TIMEOUT;
 8000d72:	2303      	movs	r3, #3
 8000d74:	e2b6      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 8000d76:	4b46      	ldr	r3, [pc, #280]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000d78:	681b      	ldr	r3, [r3, #0]
 8000d7a:	2204      	movs	r2, #4
 8000d7c:	4013      	ands	r3, r2
 8000d7e:	d0f1      	beq.n	8000d64 <HAL_RCC_OscConfig+0x20c>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8000d80:	4b43      	ldr	r3, [pc, #268]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000d82:	685b      	ldr	r3, [r3, #4]
 8000d84:	4a45      	ldr	r2, [pc, #276]	; (8000e9c <HAL_RCC_OscConfig+0x344>)
 8000d86:	4013      	ands	r3, r2
 8000d88:	0019      	movs	r1, r3
 8000d8a:	687b      	ldr	r3, [r7, #4]
 8000d8c:	691b      	ldr	r3, [r3, #16]
 8000d8e:	021a      	lsls	r2, r3, #8
 8000d90:	4b3f      	ldr	r3, [pc, #252]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000d92:	430a      	orrs	r2, r1
 8000d94:	605a      	str	r2, [r3, #4]
 8000d96:	e018      	b.n	8000dca <HAL_RCC_OscConfig+0x272>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 8000d98:	4b3d      	ldr	r3, [pc, #244]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000d9a:	681a      	ldr	r2, [r3, #0]
 8000d9c:	4b3c      	ldr	r3, [pc, #240]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000d9e:	2101      	movs	r1, #1
 8000da0:	438a      	bics	r2, r1
 8000da2:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000da4:	f7ff fc38 	bl	8000618 <HAL_GetTick>
 8000da8:	0003      	movs	r3, r0
 8000daa:	617b      	str	r3, [r7, #20]

        /* Wait till HSI is disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
 8000dac:	e008      	b.n	8000dc0 <HAL_RCC_OscConfig+0x268>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000dae:	f7ff fc33 	bl	8000618 <HAL_GetTick>
 8000db2:	0002      	movs	r2, r0
 8000db4:	697b      	ldr	r3, [r7, #20]
 8000db6:	1ad3      	subs	r3, r2, r3
 8000db8:	2b02      	cmp	r3, #2
 8000dba:	d901      	bls.n	8000dc0 <HAL_RCC_OscConfig+0x268>
          {
            return HAL_TIMEOUT;
 8000dbc:	2303      	movs	r3, #3
 8000dbe:	e291      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
 8000dc0:	4b33      	ldr	r3, [pc, #204]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000dc2:	681b      	ldr	r3, [r3, #0]
 8000dc4:	2204      	movs	r2, #4
 8000dc6:	4013      	ands	r3, r2
 8000dc8:	d1f1      	bne.n	8000dae <HAL_RCC_OscConfig+0x256>
        }
      }
    }
  }
  /*----------------------------- MSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
 8000dca:	687b      	ldr	r3, [r7, #4]
 8000dcc:	681b      	ldr	r3, [r3, #0]
 8000dce:	2210      	movs	r2, #16
 8000dd0:	4013      	ands	r3, r2
 8000dd2:	d100      	bne.n	8000dd6 <HAL_RCC_OscConfig+0x27e>
 8000dd4:	e09f      	b.n	8000f16 <HAL_RCC_OscConfig+0x3be>
  {
    /* When the MSI is used as system clock it will not be disabled */
    if((sysclk_source == RCC_CFGR_SWS_MSI) )
 8000dd6:	69fb      	ldr	r3, [r7, #28]
 8000dd8:	2b00      	cmp	r3, #0
 8000dda:	d13f      	bne.n	8000e5c <HAL_RCC_OscConfig+0x304>
    {
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
 8000ddc:	4b2c      	ldr	r3, [pc, #176]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000dde:	681a      	ldr	r2, [r3, #0]
 8000de0:	2380      	movs	r3, #128	; 0x80
 8000de2:	009b      	lsls	r3, r3, #2
 8000de4:	4013      	ands	r3, r2
 8000de6:	d005      	beq.n	8000df4 <HAL_RCC_OscConfig+0x29c>
 8000de8:	687b      	ldr	r3, [r7, #4]
 8000dea:	69db      	ldr	r3, [r3, #28]
 8000dec:	2b00      	cmp	r3, #0
 8000dee:	d101      	bne.n	8000df4 <HAL_RCC_OscConfig+0x29c>
      {
        return HAL_ERROR;
 8000df0:	2301      	movs	r3, #1
 8000df2:	e277      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
        /* Check MSICalibrationValue and MSIClockRange input parameters */
        assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));

        /* Selects the Multiple Speed oscillator (MSI) clock range .*/
        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8000df4:	4b26      	ldr	r3, [pc, #152]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000df6:	685b      	ldr	r3, [r3, #4]
 8000df8:	4a2b      	ldr	r2, [pc, #172]	; (8000ea8 <HAL_RCC_OscConfig+0x350>)
 8000dfa:	4013      	ands	r3, r2
 8000dfc:	0019      	movs	r1, r3
 8000dfe:	687b      	ldr	r3, [r7, #4]
 8000e00:	6a5a      	ldr	r2, [r3, #36]	; 0x24
 8000e02:	4b23      	ldr	r3, [pc, #140]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000e04:	430a      	orrs	r2, r1
 8000e06:	605a      	str	r2, [r3, #4]
        /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 8000e08:	4b21      	ldr	r3, [pc, #132]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000e0a:	685b      	ldr	r3, [r3, #4]
 8000e0c:	021b      	lsls	r3, r3, #8
 8000e0e:	0a19      	lsrs	r1, r3, #8
 8000e10:	687b      	ldr	r3, [r7, #4]
 8000e12:	6a1b      	ldr	r3, [r3, #32]
 8000e14:	061a      	lsls	r2, r3, #24
 8000e16:	4b1e      	ldr	r3, [pc, #120]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000e18:	430a      	orrs	r2, r1
 8000e1a:	605a      	str	r2, [r3, #4]


        /* Update the SystemCoreClock global variable */
        SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
 8000e1c:	687b      	ldr	r3, [r7, #4]
 8000e1e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8000e20:	0b5b      	lsrs	r3, r3, #13
 8000e22:	3301      	adds	r3, #1
 8000e24:	2280      	movs	r2, #128	; 0x80
 8000e26:	0212      	lsls	r2, r2, #8
 8000e28:	409a      	lsls	r2, r3
                           >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
 8000e2a:	4b19      	ldr	r3, [pc, #100]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000e2c:	68db      	ldr	r3, [r3, #12]
 8000e2e:	091b      	lsrs	r3, r3, #4
 8000e30:	210f      	movs	r1, #15
 8000e32:	400b      	ands	r3, r1
 8000e34:	491a      	ldr	r1, [pc, #104]	; (8000ea0 <HAL_RCC_OscConfig+0x348>)
 8000e36:	5ccb      	ldrb	r3, [r1, r3]
 8000e38:	40da      	lsrs	r2, r3
        SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
 8000e3a:	4b1a      	ldr	r3, [pc, #104]	; (8000ea4 <HAL_RCC_OscConfig+0x34c>)
 8000e3c:	601a      	str	r2, [r3, #0]

        /* Configure the source of time base considering new system clocks settings*/
        status = HAL_InitTick (TICK_INT_PRIORITY);
 8000e3e:	2513      	movs	r5, #19
 8000e40:	197c      	adds	r4, r7, r5
 8000e42:	2000      	movs	r0, #0
 8000e44:	f7ff fba2 	bl	800058c <HAL_InitTick>
 8000e48:	0003      	movs	r3, r0
 8000e4a:	7023      	strb	r3, [r4, #0]
        if(status != HAL_OK)
 8000e4c:	197b      	adds	r3, r7, r5
 8000e4e:	781b      	ldrb	r3, [r3, #0]
 8000e50:	2b00      	cmp	r3, #0
 8000e52:	d060      	beq.n	8000f16 <HAL_RCC_OscConfig+0x3be>
        {
          return status;
 8000e54:	2313      	movs	r3, #19
 8000e56:	18fb      	adds	r3, r7, r3
 8000e58:	781b      	ldrb	r3, [r3, #0]
 8000e5a:	e243      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
    {
      /* Check MSI State */
      assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));

      /* Check the MSI State */
      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
 8000e5c:	687b      	ldr	r3, [r7, #4]
 8000e5e:	69db      	ldr	r3, [r3, #28]
 8000e60:	2b00      	cmp	r3, #0
 8000e62:	d03e      	beq.n	8000ee2 <HAL_RCC_OscConfig+0x38a>
      {
        /* Enable the Multi Speed oscillator (MSI). */
        __HAL_RCC_MSI_ENABLE();
 8000e64:	4b0a      	ldr	r3, [pc, #40]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000e66:	681a      	ldr	r2, [r3, #0]
 8000e68:	4b09      	ldr	r3, [pc, #36]	; (8000e90 <HAL_RCC_OscConfig+0x338>)
 8000e6a:	2180      	movs	r1, #128	; 0x80
 8000e6c:	0049      	lsls	r1, r1, #1
 8000e6e:	430a      	orrs	r2, r1
 8000e70:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000e72:	f7ff fbd1 	bl	8000618 <HAL_GetTick>
 8000e76:	0003      	movs	r3, r0
 8000e78:	617b      	str	r3, [r7, #20]

        /* Wait till MSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
 8000e7a:	e017      	b.n	8000eac <HAL_RCC_OscConfig+0x354>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 8000e7c:	f7ff fbcc 	bl	8000618 <HAL_GetTick>
 8000e80:	0002      	movs	r2, r0
 8000e82:	697b      	ldr	r3, [r7, #20]
 8000e84:	1ad3      	subs	r3, r2, r3
 8000e86:	2b02      	cmp	r3, #2
 8000e88:	d910      	bls.n	8000eac <HAL_RCC_OscConfig+0x354>
          {
            return HAL_TIMEOUT;
 8000e8a:	2303      	movs	r3, #3
 8000e8c:	e22a      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
 8000e8e:	46c0      	nop			; (mov r8, r8)
 8000e90:	40021000 	.word	0x40021000
 8000e94:	fffeffff 	.word	0xfffeffff
 8000e98:	fffbffff 	.word	0xfffbffff
 8000e9c:	ffffe0ff 	.word	0xffffe0ff
 8000ea0:	080019ac 	.word	0x080019ac
 8000ea4:	20000000 	.word	0x20000000
 8000ea8:	ffff1fff 	.word	0xffff1fff
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
 8000eac:	4bc6      	ldr	r3, [pc, #792]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000eae:	681a      	ldr	r2, [r3, #0]
 8000eb0:	2380      	movs	r3, #128	; 0x80
 8000eb2:	009b      	lsls	r3, r3, #2
 8000eb4:	4013      	ands	r3, r2
 8000eb6:	d0e1      	beq.n	8000e7c <HAL_RCC_OscConfig+0x324>
        /* Check MSICalibrationValue and MSIClockRange input parameters */
        assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));

        /* Selects the Multiple Speed oscillator (MSI) clock range .*/
        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8000eb8:	4bc3      	ldr	r3, [pc, #780]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000eba:	685b      	ldr	r3, [r3, #4]
 8000ebc:	4ac3      	ldr	r2, [pc, #780]	; (80011cc <HAL_RCC_OscConfig+0x674>)
 8000ebe:	4013      	ands	r3, r2
 8000ec0:	0019      	movs	r1, r3
 8000ec2:	687b      	ldr	r3, [r7, #4]
 8000ec4:	6a5a      	ldr	r2, [r3, #36]	; 0x24
 8000ec6:	4bc0      	ldr	r3, [pc, #768]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000ec8:	430a      	orrs	r2, r1
 8000eca:	605a      	str	r2, [r3, #4]
         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 8000ecc:	4bbe      	ldr	r3, [pc, #760]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000ece:	685b      	ldr	r3, [r3, #4]
 8000ed0:	021b      	lsls	r3, r3, #8
 8000ed2:	0a19      	lsrs	r1, r3, #8
 8000ed4:	687b      	ldr	r3, [r7, #4]
 8000ed6:	6a1b      	ldr	r3, [r3, #32]
 8000ed8:	061a      	lsls	r2, r3, #24
 8000eda:	4bbb      	ldr	r3, [pc, #748]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000edc:	430a      	orrs	r2, r1
 8000ede:	605a      	str	r2, [r3, #4]
 8000ee0:	e019      	b.n	8000f16 <HAL_RCC_OscConfig+0x3be>
      }
      else
      {
        /* Disable the Multi Speed oscillator (MSI). */
        __HAL_RCC_MSI_DISABLE();
 8000ee2:	4bb9      	ldr	r3, [pc, #740]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000ee4:	681a      	ldr	r2, [r3, #0]
 8000ee6:	4bb8      	ldr	r3, [pc, #736]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000ee8:	49b9      	ldr	r1, [pc, #740]	; (80011d0 <HAL_RCC_OscConfig+0x678>)
 8000eea:	400a      	ands	r2, r1
 8000eec:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000eee:	f7ff fb93 	bl	8000618 <HAL_GetTick>
 8000ef2:	0003      	movs	r3, r0
 8000ef4:	617b      	str	r3, [r7, #20]

        /* Wait till MSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
 8000ef6:	e008      	b.n	8000f0a <HAL_RCC_OscConfig+0x3b2>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 8000ef8:	f7ff fb8e 	bl	8000618 <HAL_GetTick>
 8000efc:	0002      	movs	r2, r0
 8000efe:	697b      	ldr	r3, [r7, #20]
 8000f00:	1ad3      	subs	r3, r2, r3
 8000f02:	2b02      	cmp	r3, #2
 8000f04:	d901      	bls.n	8000f0a <HAL_RCC_OscConfig+0x3b2>
          {
            return HAL_TIMEOUT;
 8000f06:	2303      	movs	r3, #3
 8000f08:	e1ec      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
 8000f0a:	4baf      	ldr	r3, [pc, #700]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000f0c:	681a      	ldr	r2, [r3, #0]
 8000f0e:	2380      	movs	r3, #128	; 0x80
 8000f10:	009b      	lsls	r3, r3, #2
 8000f12:	4013      	ands	r3, r2
 8000f14:	d1f0      	bne.n	8000ef8 <HAL_RCC_OscConfig+0x3a0>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8000f16:	687b      	ldr	r3, [r7, #4]
 8000f18:	681b      	ldr	r3, [r3, #0]
 8000f1a:	2208      	movs	r2, #8
 8000f1c:	4013      	ands	r3, r2
 8000f1e:	d036      	beq.n	8000f8e <HAL_RCC_OscConfig+0x436>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8000f20:	687b      	ldr	r3, [r7, #4]
 8000f22:	695b      	ldr	r3, [r3, #20]
 8000f24:	2b00      	cmp	r3, #0
 8000f26:	d019      	beq.n	8000f5c <HAL_RCC_OscConfig+0x404>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 8000f28:	4ba7      	ldr	r3, [pc, #668]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000f2a:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 8000f2c:	4ba6      	ldr	r3, [pc, #664]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000f2e:	2101      	movs	r1, #1
 8000f30:	430a      	orrs	r2, r1
 8000f32:	651a      	str	r2, [r3, #80]	; 0x50

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8000f34:	f7ff fb70 	bl	8000618 <HAL_GetTick>
 8000f38:	0003      	movs	r3, r0
 8000f3a:	617b      	str	r3, [r7, #20]

      /* Wait till LSI is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
 8000f3c:	e008      	b.n	8000f50 <HAL_RCC_OscConfig+0x3f8>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000f3e:	f7ff fb6b 	bl	8000618 <HAL_GetTick>
 8000f42:	0002      	movs	r2, r0
 8000f44:	697b      	ldr	r3, [r7, #20]
 8000f46:	1ad3      	subs	r3, r2, r3
 8000f48:	2b02      	cmp	r3, #2
 8000f4a:	d901      	bls.n	8000f50 <HAL_RCC_OscConfig+0x3f8>
        {
          return HAL_TIMEOUT;
 8000f4c:	2303      	movs	r3, #3
 8000f4e:	e1c9      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
 8000f50:	4b9d      	ldr	r3, [pc, #628]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000f52:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 8000f54:	2202      	movs	r2, #2
 8000f56:	4013      	ands	r3, r2
 8000f58:	d0f1      	beq.n	8000f3e <HAL_RCC_OscConfig+0x3e6>
 8000f5a:	e018      	b.n	8000f8e <HAL_RCC_OscConfig+0x436>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8000f5c:	4b9a      	ldr	r3, [pc, #616]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000f5e:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 8000f60:	4b99      	ldr	r3, [pc, #612]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000f62:	2101      	movs	r1, #1
 8000f64:	438a      	bics	r2, r1
 8000f66:	651a      	str	r2, [r3, #80]	; 0x50

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8000f68:	f7ff fb56 	bl	8000618 <HAL_GetTick>
 8000f6c:	0003      	movs	r3, r0
 8000f6e:	617b      	str	r3, [r7, #20]

      /* Wait till LSI is disabled */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
 8000f70:	e008      	b.n	8000f84 <HAL_RCC_OscConfig+0x42c>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000f72:	f7ff fb51 	bl	8000618 <HAL_GetTick>
 8000f76:	0002      	movs	r2, r0
 8000f78:	697b      	ldr	r3, [r7, #20]
 8000f7a:	1ad3      	subs	r3, r2, r3
 8000f7c:	2b02      	cmp	r3, #2
 8000f7e:	d901      	bls.n	8000f84 <HAL_RCC_OscConfig+0x42c>
        {
          return HAL_TIMEOUT;
 8000f80:	2303      	movs	r3, #3
 8000f82:	e1af      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
 8000f84:	4b90      	ldr	r3, [pc, #576]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000f86:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 8000f88:	2202      	movs	r2, #2
 8000f8a:	4013      	ands	r3, r2
 8000f8c:	d1f1      	bne.n	8000f72 <HAL_RCC_OscConfig+0x41a>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8000f8e:	687b      	ldr	r3, [r7, #4]
 8000f90:	681b      	ldr	r3, [r3, #0]
 8000f92:	2204      	movs	r2, #4
 8000f94:	4013      	ands	r3, r2
 8000f96:	d100      	bne.n	8000f9a <HAL_RCC_OscConfig+0x442>
 8000f98:	e0af      	b.n	80010fa <HAL_RCC_OscConfig+0x5a2>
  {
    FlagStatus       pwrclkchanged = RESET;
 8000f9a:	2323      	movs	r3, #35	; 0x23
 8000f9c:	18fb      	adds	r3, r7, r3
 8000f9e:	2200      	movs	r2, #0
 8000fa0:	701a      	strb	r2, [r3, #0]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8000fa2:	4b89      	ldr	r3, [pc, #548]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000fa4:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 8000fa6:	2380      	movs	r3, #128	; 0x80
 8000fa8:	055b      	lsls	r3, r3, #21
 8000faa:	4013      	ands	r3, r2
 8000fac:	d10a      	bne.n	8000fc4 <HAL_RCC_OscConfig+0x46c>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8000fae:	4b86      	ldr	r3, [pc, #536]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000fb0:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 8000fb2:	4b85      	ldr	r3, [pc, #532]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8000fb4:	2180      	movs	r1, #128	; 0x80
 8000fb6:	0549      	lsls	r1, r1, #21
 8000fb8:	430a      	orrs	r2, r1
 8000fba:	639a      	str	r2, [r3, #56]	; 0x38
      pwrclkchanged = SET;
 8000fbc:	2323      	movs	r3, #35	; 0x23
 8000fbe:	18fb      	adds	r3, r7, r3
 8000fc0:	2201      	movs	r2, #1
 8000fc2:	701a      	strb	r2, [r3, #0]
    }

    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000fc4:	4b83      	ldr	r3, [pc, #524]	; (80011d4 <HAL_RCC_OscConfig+0x67c>)
 8000fc6:	681a      	ldr	r2, [r3, #0]
 8000fc8:	2380      	movs	r3, #128	; 0x80
 8000fca:	005b      	lsls	r3, r3, #1
 8000fcc:	4013      	ands	r3, r2
 8000fce:	d11a      	bne.n	8001006 <HAL_RCC_OscConfig+0x4ae>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8000fd0:	4b80      	ldr	r3, [pc, #512]	; (80011d4 <HAL_RCC_OscConfig+0x67c>)
 8000fd2:	681a      	ldr	r2, [r3, #0]
 8000fd4:	4b7f      	ldr	r3, [pc, #508]	; (80011d4 <HAL_RCC_OscConfig+0x67c>)
 8000fd6:	2180      	movs	r1, #128	; 0x80
 8000fd8:	0049      	lsls	r1, r1, #1
 8000fda:	430a      	orrs	r2, r1
 8000fdc:	601a      	str	r2, [r3, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 8000fde:	f7ff fb1b 	bl	8000618 <HAL_GetTick>
 8000fe2:	0003      	movs	r3, r0
 8000fe4:	617b      	str	r3, [r7, #20]

      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000fe6:	e008      	b.n	8000ffa <HAL_RCC_OscConfig+0x4a2>
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8000fe8:	f7ff fb16 	bl	8000618 <HAL_GetTick>
 8000fec:	0002      	movs	r2, r0
 8000fee:	697b      	ldr	r3, [r7, #20]
 8000ff0:	1ad3      	subs	r3, r2, r3
 8000ff2:	2b64      	cmp	r3, #100	; 0x64
 8000ff4:	d901      	bls.n	8000ffa <HAL_RCC_OscConfig+0x4a2>
        {
          return HAL_TIMEOUT;
 8000ff6:	2303      	movs	r3, #3
 8000ff8:	e174      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000ffa:	4b76      	ldr	r3, [pc, #472]	; (80011d4 <HAL_RCC_OscConfig+0x67c>)
 8000ffc:	681a      	ldr	r2, [r3, #0]
 8000ffe:	2380      	movs	r3, #128	; 0x80
 8001000:	005b      	lsls	r3, r3, #1
 8001002:	4013      	ands	r3, r2
 8001004:	d0f0      	beq.n	8000fe8 <HAL_RCC_OscConfig+0x490>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8001006:	687b      	ldr	r3, [r7, #4]
 8001008:	689a      	ldr	r2, [r3, #8]
 800100a:	2380      	movs	r3, #128	; 0x80
 800100c:	005b      	lsls	r3, r3, #1
 800100e:	429a      	cmp	r2, r3
 8001010:	d107      	bne.n	8001022 <HAL_RCC_OscConfig+0x4ca>
 8001012:	4b6d      	ldr	r3, [pc, #436]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001014:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 8001016:	4b6c      	ldr	r3, [pc, #432]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001018:	2180      	movs	r1, #128	; 0x80
 800101a:	0049      	lsls	r1, r1, #1
 800101c:	430a      	orrs	r2, r1
 800101e:	651a      	str	r2, [r3, #80]	; 0x50
 8001020:	e031      	b.n	8001086 <HAL_RCC_OscConfig+0x52e>
 8001022:	687b      	ldr	r3, [r7, #4]
 8001024:	689b      	ldr	r3, [r3, #8]
 8001026:	2b00      	cmp	r3, #0
 8001028:	d10c      	bne.n	8001044 <HAL_RCC_OscConfig+0x4ec>
 800102a:	4b67      	ldr	r3, [pc, #412]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 800102c:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 800102e:	4b66      	ldr	r3, [pc, #408]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001030:	4967      	ldr	r1, [pc, #412]	; (80011d0 <HAL_RCC_OscConfig+0x678>)
 8001032:	400a      	ands	r2, r1
 8001034:	651a      	str	r2, [r3, #80]	; 0x50
 8001036:	4b64      	ldr	r3, [pc, #400]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001038:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 800103a:	4b63      	ldr	r3, [pc, #396]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 800103c:	4966      	ldr	r1, [pc, #408]	; (80011d8 <HAL_RCC_OscConfig+0x680>)
 800103e:	400a      	ands	r2, r1
 8001040:	651a      	str	r2, [r3, #80]	; 0x50
 8001042:	e020      	b.n	8001086 <HAL_RCC_OscConfig+0x52e>
 8001044:	687b      	ldr	r3, [r7, #4]
 8001046:	689a      	ldr	r2, [r3, #8]
 8001048:	23a0      	movs	r3, #160	; 0xa0
 800104a:	00db      	lsls	r3, r3, #3
 800104c:	429a      	cmp	r2, r3
 800104e:	d10e      	bne.n	800106e <HAL_RCC_OscConfig+0x516>
 8001050:	4b5d      	ldr	r3, [pc, #372]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001052:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 8001054:	4b5c      	ldr	r3, [pc, #368]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001056:	2180      	movs	r1, #128	; 0x80
 8001058:	00c9      	lsls	r1, r1, #3
 800105a:	430a      	orrs	r2, r1
 800105c:	651a      	str	r2, [r3, #80]	; 0x50
 800105e:	4b5a      	ldr	r3, [pc, #360]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001060:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 8001062:	4b59      	ldr	r3, [pc, #356]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001064:	2180      	movs	r1, #128	; 0x80
 8001066:	0049      	lsls	r1, r1, #1
 8001068:	430a      	orrs	r2, r1
 800106a:	651a      	str	r2, [r3, #80]	; 0x50
 800106c:	e00b      	b.n	8001086 <HAL_RCC_OscConfig+0x52e>
 800106e:	4b56      	ldr	r3, [pc, #344]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001070:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 8001072:	4b55      	ldr	r3, [pc, #340]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001074:	4956      	ldr	r1, [pc, #344]	; (80011d0 <HAL_RCC_OscConfig+0x678>)
 8001076:	400a      	ands	r2, r1
 8001078:	651a      	str	r2, [r3, #80]	; 0x50
 800107a:	4b53      	ldr	r3, [pc, #332]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 800107c:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 800107e:	4b52      	ldr	r3, [pc, #328]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001080:	4955      	ldr	r1, [pc, #340]	; (80011d8 <HAL_RCC_OscConfig+0x680>)
 8001082:	400a      	ands	r2, r1
 8001084:	651a      	str	r2, [r3, #80]	; 0x50
    /* Check the LSE State */
    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 8001086:	687b      	ldr	r3, [r7, #4]
 8001088:	689b      	ldr	r3, [r3, #8]
 800108a:	2b00      	cmp	r3, #0
 800108c:	d015      	beq.n	80010ba <HAL_RCC_OscConfig+0x562>
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 800108e:	f7ff fac3 	bl	8000618 <HAL_GetTick>
 8001092:	0003      	movs	r3, r0
 8001094:	617b      	str	r3, [r7, #20]

      /* Wait till LSE is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 8001096:	e009      	b.n	80010ac <HAL_RCC_OscConfig+0x554>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8001098:	f7ff fabe 	bl	8000618 <HAL_GetTick>
 800109c:	0002      	movs	r2, r0
 800109e:	697b      	ldr	r3, [r7, #20]
 80010a0:	1ad3      	subs	r3, r2, r3
 80010a2:	4a4e      	ldr	r2, [pc, #312]	; (80011dc <HAL_RCC_OscConfig+0x684>)
 80010a4:	4293      	cmp	r3, r2
 80010a6:	d901      	bls.n	80010ac <HAL_RCC_OscConfig+0x554>
        {
          return HAL_TIMEOUT;
 80010a8:	2303      	movs	r3, #3
 80010aa:	e11b      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 80010ac:	4b46      	ldr	r3, [pc, #280]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 80010ae:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 80010b0:	2380      	movs	r3, #128	; 0x80
 80010b2:	009b      	lsls	r3, r3, #2
 80010b4:	4013      	ands	r3, r2
 80010b6:	d0ef      	beq.n	8001098 <HAL_RCC_OscConfig+0x540>
 80010b8:	e014      	b.n	80010e4 <HAL_RCC_OscConfig+0x58c>
      }
    }
    else
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 80010ba:	f7ff faad 	bl	8000618 <HAL_GetTick>
 80010be:	0003      	movs	r3, r0
 80010c0:	617b      	str	r3, [r7, #20]

      /* Wait till LSE is disabled */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
 80010c2:	e009      	b.n	80010d8 <HAL_RCC_OscConfig+0x580>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 80010c4:	f7ff faa8 	bl	8000618 <HAL_GetTick>
 80010c8:	0002      	movs	r2, r0
 80010ca:	697b      	ldr	r3, [r7, #20]
 80010cc:	1ad3      	subs	r3, r2, r3
 80010ce:	4a43      	ldr	r2, [pc, #268]	; (80011dc <HAL_RCC_OscConfig+0x684>)
 80010d0:	4293      	cmp	r3, r2
 80010d2:	d901      	bls.n	80010d8 <HAL_RCC_OscConfig+0x580>
        {
          return HAL_TIMEOUT;
 80010d4:	2303      	movs	r3, #3
 80010d6:	e105      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
 80010d8:	4b3b      	ldr	r3, [pc, #236]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 80010da:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 80010dc:	2380      	movs	r3, #128	; 0x80
 80010de:	009b      	lsls	r3, r3, #2
 80010e0:	4013      	ands	r3, r2
 80010e2:	d1ef      	bne.n	80010c4 <HAL_RCC_OscConfig+0x56c>
        }
      }
    }

    /* Require to disable power clock if necessary */
    if(pwrclkchanged == SET)
 80010e4:	2323      	movs	r3, #35	; 0x23
 80010e6:	18fb      	adds	r3, r7, r3
 80010e8:	781b      	ldrb	r3, [r3, #0]
 80010ea:	2b01      	cmp	r3, #1
 80010ec:	d105      	bne.n	80010fa <HAL_RCC_OscConfig+0x5a2>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 80010ee:	4b36      	ldr	r3, [pc, #216]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 80010f0:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 80010f2:	4b35      	ldr	r3, [pc, #212]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 80010f4:	493a      	ldr	r1, [pc, #232]	; (80011e0 <HAL_RCC_OscConfig+0x688>)
 80010f6:	400a      	ands	r2, r1
 80010f8:	639a      	str	r2, [r3, #56]	; 0x38
    }
  }

#if defined(RCC_HSI48_SUPPORT)
  /*----------------------------- HSI48 Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
 80010fa:	687b      	ldr	r3, [r7, #4]
 80010fc:	681b      	ldr	r3, [r3, #0]
 80010fe:	2220      	movs	r2, #32
 8001100:	4013      	ands	r3, r2
 8001102:	d049      	beq.n	8001198 <HAL_RCC_OscConfig+0x640>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));

      /* Check the HSI48 State */
      if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
 8001104:	687b      	ldr	r3, [r7, #4]
 8001106:	699b      	ldr	r3, [r3, #24]
 8001108:	2b00      	cmp	r3, #0
 800110a:	d026      	beq.n	800115a <HAL_RCC_OscConfig+0x602>
      {
        /* Enable the Internal High Speed oscillator (HSI48). */
        __HAL_RCC_HSI48_ENABLE();
 800110c:	4b2e      	ldr	r3, [pc, #184]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 800110e:	689a      	ldr	r2, [r3, #8]
 8001110:	4b2d      	ldr	r3, [pc, #180]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001112:	2101      	movs	r1, #1
 8001114:	430a      	orrs	r2, r1
 8001116:	609a      	str	r2, [r3, #8]
 8001118:	4b2b      	ldr	r3, [pc, #172]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 800111a:	6b5a      	ldr	r2, [r3, #52]	; 0x34
 800111c:	4b2a      	ldr	r3, [pc, #168]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 800111e:	2101      	movs	r1, #1
 8001120:	430a      	orrs	r2, r1
 8001122:	635a      	str	r2, [r3, #52]	; 0x34
 8001124:	4b2f      	ldr	r3, [pc, #188]	; (80011e4 <HAL_RCC_OscConfig+0x68c>)
 8001126:	6a1a      	ldr	r2, [r3, #32]
 8001128:	4b2e      	ldr	r3, [pc, #184]	; (80011e4 <HAL_RCC_OscConfig+0x68c>)
 800112a:	2180      	movs	r1, #128	; 0x80
 800112c:	0189      	lsls	r1, r1, #6
 800112e:	430a      	orrs	r2, r1
 8001130:	621a      	str	r2, [r3, #32]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001132:	f7ff fa71 	bl	8000618 <HAL_GetTick>
 8001136:	0003      	movs	r3, r0
 8001138:	617b      	str	r3, [r7, #20]

        /* Wait till HSI48 is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
 800113a:	e008      	b.n	800114e <HAL_RCC_OscConfig+0x5f6>
        {
          if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
 800113c:	f7ff fa6c 	bl	8000618 <HAL_GetTick>
 8001140:	0002      	movs	r2, r0
 8001142:	697b      	ldr	r3, [r7, #20]
 8001144:	1ad3      	subs	r3, r2, r3
 8001146:	2b02      	cmp	r3, #2
 8001148:	d901      	bls.n	800114e <HAL_RCC_OscConfig+0x5f6>
          {
            return HAL_TIMEOUT;
 800114a:	2303      	movs	r3, #3
 800114c:	e0ca      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
 800114e:	4b1e      	ldr	r3, [pc, #120]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001150:	689b      	ldr	r3, [r3, #8]
 8001152:	2202      	movs	r2, #2
 8001154:	4013      	ands	r3, r2
 8001156:	d0f1      	beq.n	800113c <HAL_RCC_OscConfig+0x5e4>
 8001158:	e01e      	b.n	8001198 <HAL_RCC_OscConfig+0x640>
        }
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI48). */
        __HAL_RCC_HSI48_DISABLE();
 800115a:	4b1b      	ldr	r3, [pc, #108]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 800115c:	689a      	ldr	r2, [r3, #8]
 800115e:	4b1a      	ldr	r3, [pc, #104]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001160:	2101      	movs	r1, #1
 8001162:	438a      	bics	r2, r1
 8001164:	609a      	str	r2, [r3, #8]
 8001166:	4b1f      	ldr	r3, [pc, #124]	; (80011e4 <HAL_RCC_OscConfig+0x68c>)
 8001168:	6a1a      	ldr	r2, [r3, #32]
 800116a:	4b1e      	ldr	r3, [pc, #120]	; (80011e4 <HAL_RCC_OscConfig+0x68c>)
 800116c:	491e      	ldr	r1, [pc, #120]	; (80011e8 <HAL_RCC_OscConfig+0x690>)
 800116e:	400a      	ands	r2, r1
 8001170:	621a      	str	r2, [r3, #32]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001172:	f7ff fa51 	bl	8000618 <HAL_GetTick>
 8001176:	0003      	movs	r3, r0
 8001178:	617b      	str	r3, [r7, #20]

        /* Wait till HSI48 is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
 800117a:	e008      	b.n	800118e <HAL_RCC_OscConfig+0x636>
        {
          if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
 800117c:	f7ff fa4c 	bl	8000618 <HAL_GetTick>
 8001180:	0002      	movs	r2, r0
 8001182:	697b      	ldr	r3, [r7, #20]
 8001184:	1ad3      	subs	r3, r2, r3
 8001186:	2b02      	cmp	r3, #2
 8001188:	d901      	bls.n	800118e <HAL_RCC_OscConfig+0x636>
          {
            return HAL_TIMEOUT;
 800118a:	2303      	movs	r3, #3
 800118c:	e0aa      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
 800118e:	4b0e      	ldr	r3, [pc, #56]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 8001190:	689b      	ldr	r3, [r3, #8]
 8001192:	2202      	movs	r2, #2
 8001194:	4013      	ands	r3, r2
 8001196:	d1f1      	bne.n	800117c <HAL_RCC_OscConfig+0x624>
#endif /* RCC_HSI48_SUPPORT */

  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8001198:	687b      	ldr	r3, [r7, #4]
 800119a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800119c:	2b00      	cmp	r3, #0
 800119e:	d100      	bne.n	80011a2 <HAL_RCC_OscConfig+0x64a>
 80011a0:	e09f      	b.n	80012e2 <HAL_RCC_OscConfig+0x78a>
  {
    /* Check if the PLL is used as system clock or not */
    if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 80011a2:	69fb      	ldr	r3, [r7, #28]
 80011a4:	2b0c      	cmp	r3, #12
 80011a6:	d100      	bne.n	80011aa <HAL_RCC_OscConfig+0x652>
 80011a8:	e078      	b.n	800129c <HAL_RCC_OscConfig+0x744>
    {
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 80011aa:	687b      	ldr	r3, [r7, #4]
 80011ac:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80011ae:	2b02      	cmp	r3, #2
 80011b0:	d159      	bne.n	8001266 <HAL_RCC_OscConfig+0x70e>
        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
        assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 80011b2:	4b05      	ldr	r3, [pc, #20]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 80011b4:	681a      	ldr	r2, [r3, #0]
 80011b6:	4b04      	ldr	r3, [pc, #16]	; (80011c8 <HAL_RCC_OscConfig+0x670>)
 80011b8:	490c      	ldr	r1, [pc, #48]	; (80011ec <HAL_RCC_OscConfig+0x694>)
 80011ba:	400a      	ands	r2, r1
 80011bc:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80011be:	f7ff fa2b 	bl	8000618 <HAL_GetTick>
 80011c2:	0003      	movs	r3, r0
 80011c4:	617b      	str	r3, [r7, #20]

        /* Wait till PLL is disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != 0U)
 80011c6:	e01c      	b.n	8001202 <HAL_RCC_OscConfig+0x6aa>
 80011c8:	40021000 	.word	0x40021000
 80011cc:	ffff1fff 	.word	0xffff1fff
 80011d0:	fffffeff 	.word	0xfffffeff
 80011d4:	40007000 	.word	0x40007000
 80011d8:	fffffbff 	.word	0xfffffbff
 80011dc:	00001388 	.word	0x00001388
 80011e0:	efffffff 	.word	0xefffffff
 80011e4:	40010000 	.word	0x40010000
 80011e8:	ffffdfff 	.word	0xffffdfff
 80011ec:	feffffff 	.word	0xfeffffff
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 80011f0:	f7ff fa12 	bl	8000618 <HAL_GetTick>
 80011f4:	0002      	movs	r2, r0
 80011f6:	697b      	ldr	r3, [r7, #20]
 80011f8:	1ad3      	subs	r3, r2, r3
 80011fa:	2b02      	cmp	r3, #2
 80011fc:	d901      	bls.n	8001202 <HAL_RCC_OscConfig+0x6aa>
          {
            return HAL_TIMEOUT;
 80011fe:	2303      	movs	r3, #3
 8001200:	e070      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != 0U)
 8001202:	4b3a      	ldr	r3, [pc, #232]	; (80012ec <HAL_RCC_OscConfig+0x794>)
 8001204:	681a      	ldr	r2, [r3, #0]
 8001206:	2380      	movs	r3, #128	; 0x80
 8001208:	049b      	lsls	r3, r3, #18
 800120a:	4013      	ands	r3, r2
 800120c:	d1f0      	bne.n	80011f0 <HAL_RCC_OscConfig+0x698>
          }
        }

        /* Configure the main PLL clock source, multiplication and division factors. */
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 800120e:	4b37      	ldr	r3, [pc, #220]	; (80012ec <HAL_RCC_OscConfig+0x794>)
 8001210:	68db      	ldr	r3, [r3, #12]
 8001212:	4a37      	ldr	r2, [pc, #220]	; (80012f0 <HAL_RCC_OscConfig+0x798>)
 8001214:	4013      	ands	r3, r2
 8001216:	0019      	movs	r1, r3
 8001218:	687b      	ldr	r3, [r7, #4]
 800121a:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 800121c:	687b      	ldr	r3, [r7, #4]
 800121e:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001220:	431a      	orrs	r2, r3
 8001222:	687b      	ldr	r3, [r7, #4]
 8001224:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8001226:	431a      	orrs	r2, r3
 8001228:	4b30      	ldr	r3, [pc, #192]	; (80012ec <HAL_RCC_OscConfig+0x794>)
 800122a:	430a      	orrs	r2, r1
 800122c:	60da      	str	r2, [r3, #12]
                             RCC_OscInitStruct->PLL.PLLMUL,
                             RCC_OscInitStruct->PLL.PLLDIV);
        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 800122e:	4b2f      	ldr	r3, [pc, #188]	; (80012ec <HAL_RCC_OscConfig+0x794>)
 8001230:	681a      	ldr	r2, [r3, #0]
 8001232:	4b2e      	ldr	r3, [pc, #184]	; (80012ec <HAL_RCC_OscConfig+0x794>)
 8001234:	2180      	movs	r1, #128	; 0x80
 8001236:	0449      	lsls	r1, r1, #17
 8001238:	430a      	orrs	r2, r1
 800123a:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 800123c:	f7ff f9ec 	bl	8000618 <HAL_GetTick>
 8001240:	0003      	movs	r3, r0
 8001242:	617b      	str	r3, [r7, #20]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == 0U)
 8001244:	e008      	b.n	8001258 <HAL_RCC_OscConfig+0x700>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8001246:	f7ff f9e7 	bl	8000618 <HAL_GetTick>
 800124a:	0002      	movs	r2, r0
 800124c:	697b      	ldr	r3, [r7, #20]
 800124e:	1ad3      	subs	r3, r2, r3
 8001250:	2b02      	cmp	r3, #2
 8001252:	d901      	bls.n	8001258 <HAL_RCC_OscConfig+0x700>
          {
            return HAL_TIMEOUT;
 8001254:	2303      	movs	r3, #3
 8001256:	e045      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == 0U)
 8001258:	4b24      	ldr	r3, [pc, #144]	; (80012ec <HAL_RCC_OscConfig+0x794>)
 800125a:	681a      	ldr	r2, [r3, #0]
 800125c:	2380      	movs	r3, #128	; 0x80
 800125e:	049b      	lsls	r3, r3, #18
 8001260:	4013      	ands	r3, r2
 8001262:	d0f0      	beq.n	8001246 <HAL_RCC_OscConfig+0x6ee>
 8001264:	e03d      	b.n	80012e2 <HAL_RCC_OscConfig+0x78a>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8001266:	4b21      	ldr	r3, [pc, #132]	; (80012ec <HAL_RCC_OscConfig+0x794>)
 8001268:	681a      	ldr	r2, [r3, #0]
 800126a:	4b20      	ldr	r3, [pc, #128]	; (80012ec <HAL_RCC_OscConfig+0x794>)
 800126c:	4921      	ldr	r1, [pc, #132]	; (80012f4 <HAL_RCC_OscConfig+0x79c>)
 800126e:	400a      	ands	r2, r1
 8001270:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001272:	f7ff f9d1 	bl	8000618 <HAL_GetTick>
 8001276:	0003      	movs	r3, r0
 8001278:	617b      	str	r3, [r7, #20]

        /* Wait till PLL is disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != 0U)
 800127a:	e008      	b.n	800128e <HAL_RCC_OscConfig+0x736>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 800127c:	f7ff f9cc 	bl	8000618 <HAL_GetTick>
 8001280:	0002      	movs	r2, r0
 8001282:	697b      	ldr	r3, [r7, #20]
 8001284:	1ad3      	subs	r3, r2, r3
 8001286:	2b02      	cmp	r3, #2
 8001288:	d901      	bls.n	800128e <HAL_RCC_OscConfig+0x736>
          {
            return HAL_TIMEOUT;
 800128a:	2303      	movs	r3, #3
 800128c:	e02a      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != 0U)
 800128e:	4b17      	ldr	r3, [pc, #92]	; (80012ec <HAL_RCC_OscConfig+0x794>)
 8001290:	681a      	ldr	r2, [r3, #0]
 8001292:	2380      	movs	r3, #128	; 0x80
 8001294:	049b      	lsls	r3, r3, #18
 8001296:	4013      	ands	r3, r2
 8001298:	d1f0      	bne.n	800127c <HAL_RCC_OscConfig+0x724>
 800129a:	e022      	b.n	80012e2 <HAL_RCC_OscConfig+0x78a>
      }
    }
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 800129c:	687b      	ldr	r3, [r7, #4]
 800129e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80012a0:	2b01      	cmp	r3, #1
 80012a2:	d101      	bne.n	80012a8 <HAL_RCC_OscConfig+0x750>
      {
        return HAL_ERROR;
 80012a4:	2301      	movs	r3, #1
 80012a6:	e01d      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
      }
      else
      {
        /* Do not return HAL_ERROR if request repeats the current configuration */
        pll_config = RCC->CFGR;
 80012a8:	4b10      	ldr	r3, [pc, #64]	; (80012ec <HAL_RCC_OscConfig+0x794>)
 80012aa:	68db      	ldr	r3, [r3, #12]
 80012ac:	61bb      	str	r3, [r7, #24]
        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 80012ae:	69ba      	ldr	r2, [r7, #24]
 80012b0:	2380      	movs	r3, #128	; 0x80
 80012b2:	025b      	lsls	r3, r3, #9
 80012b4:	401a      	ands	r2, r3
 80012b6:	687b      	ldr	r3, [r7, #4]
 80012b8:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80012ba:	429a      	cmp	r2, r3
 80012bc:	d10f      	bne.n	80012de <HAL_RCC_OscConfig+0x786>
           (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
 80012be:	69ba      	ldr	r2, [r7, #24]
 80012c0:	23f0      	movs	r3, #240	; 0xf0
 80012c2:	039b      	lsls	r3, r3, #14
 80012c4:	401a      	ands	r2, r3
 80012c6:	687b      	ldr	r3, [r7, #4]
 80012c8:	6b1b      	ldr	r3, [r3, #48]	; 0x30
        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 80012ca:	429a      	cmp	r2, r3
 80012cc:	d107      	bne.n	80012de <HAL_RCC_OscConfig+0x786>
           (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
 80012ce:	69ba      	ldr	r2, [r7, #24]
 80012d0:	23c0      	movs	r3, #192	; 0xc0
 80012d2:	041b      	lsls	r3, r3, #16
 80012d4:	401a      	ands	r2, r3
 80012d6:	687b      	ldr	r3, [r7, #4]
 80012d8:	6b5b      	ldr	r3, [r3, #52]	; 0x34
           (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
 80012da:	429a      	cmp	r2, r3
 80012dc:	d001      	beq.n	80012e2 <HAL_RCC_OscConfig+0x78a>
        {
          return HAL_ERROR;
 80012de:	2301      	movs	r3, #1
 80012e0:	e000      	b.n	80012e4 <HAL_RCC_OscConfig+0x78c>
        }
      }
    }
  }

  return HAL_OK;
 80012e2:	2300      	movs	r3, #0
}
 80012e4:	0018      	movs	r0, r3
 80012e6:	46bd      	mov	sp, r7
 80012e8:	b00a      	add	sp, #40	; 0x28
 80012ea:	bdb0      	pop	{r4, r5, r7, pc}
 80012ec:	40021000 	.word	0x40021000
 80012f0:	ff02ffff 	.word	0xff02ffff
 80012f4:	feffffff 	.word	0xfeffffff

080012f8 <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 80012f8:	b5b0      	push	{r4, r5, r7, lr}
 80012fa:	b084      	sub	sp, #16
 80012fc:	af00      	add	r7, sp, #0
 80012fe:	6078      	str	r0, [r7, #4]
 8001300:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;
  HAL_StatusTypeDef status;

  /* Check the parameters */
  if(RCC_ClkInitStruct == NULL)
 8001302:	687b      	ldr	r3, [r7, #4]
 8001304:	2b00      	cmp	r3, #0
 8001306:	d101      	bne.n	800130c <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 8001308:	2301      	movs	r3, #1
 800130a:	e10d      	b.n	8001528 <HAL_RCC_ClockConfig+0x230>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
  must be correctly programmed according to the frequency of the CPU clock
  (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 800130c:	4b88      	ldr	r3, [pc, #544]	; (8001530 <HAL_RCC_ClockConfig+0x238>)
 800130e:	681b      	ldr	r3, [r3, #0]
 8001310:	2201      	movs	r2, #1
 8001312:	4013      	ands	r3, r2
 8001314:	683a      	ldr	r2, [r7, #0]
 8001316:	429a      	cmp	r2, r3
 8001318:	d911      	bls.n	800133e <HAL_RCC_ClockConfig+0x46>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 800131a:	4b85      	ldr	r3, [pc, #532]	; (8001530 <HAL_RCC_ClockConfig+0x238>)
 800131c:	681b      	ldr	r3, [r3, #0]
 800131e:	2201      	movs	r2, #1
 8001320:	4393      	bics	r3, r2
 8001322:	0019      	movs	r1, r3
 8001324:	4b82      	ldr	r3, [pc, #520]	; (8001530 <HAL_RCC_ClockConfig+0x238>)
 8001326:	683a      	ldr	r2, [r7, #0]
 8001328:	430a      	orrs	r2, r1
 800132a:	601a      	str	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 800132c:	4b80      	ldr	r3, [pc, #512]	; (8001530 <HAL_RCC_ClockConfig+0x238>)
 800132e:	681b      	ldr	r3, [r3, #0]
 8001330:	2201      	movs	r2, #1
 8001332:	4013      	ands	r3, r2
 8001334:	683a      	ldr	r2, [r7, #0]
 8001336:	429a      	cmp	r2, r3
 8001338:	d001      	beq.n	800133e <HAL_RCC_ClockConfig+0x46>
    {
      return HAL_ERROR;
 800133a:	2301      	movs	r3, #1
 800133c:	e0f4      	b.n	8001528 <HAL_RCC_ClockConfig+0x230>
    }
  }

  /*-------------------------- HCLK Configuration --------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 800133e:	687b      	ldr	r3, [r7, #4]
 8001340:	681b      	ldr	r3, [r3, #0]
 8001342:	2202      	movs	r2, #2
 8001344:	4013      	ands	r3, r2
 8001346:	d009      	beq.n	800135c <HAL_RCC_ClockConfig+0x64>
  {
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8001348:	4b7a      	ldr	r3, [pc, #488]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 800134a:	68db      	ldr	r3, [r3, #12]
 800134c:	22f0      	movs	r2, #240	; 0xf0
 800134e:	4393      	bics	r3, r2
 8001350:	0019      	movs	r1, r3
 8001352:	687b      	ldr	r3, [r7, #4]
 8001354:	689a      	ldr	r2, [r3, #8]
 8001356:	4b77      	ldr	r3, [pc, #476]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 8001358:	430a      	orrs	r2, r1
 800135a:	60da      	str	r2, [r3, #12]
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 800135c:	687b      	ldr	r3, [r7, #4]
 800135e:	681b      	ldr	r3, [r3, #0]
 8001360:	2201      	movs	r2, #1
 8001362:	4013      	ands	r3, r2
 8001364:	d100      	bne.n	8001368 <HAL_RCC_ClockConfig+0x70>
 8001366:	e089      	b.n	800147c <HAL_RCC_ClockConfig+0x184>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8001368:	687b      	ldr	r3, [r7, #4]
 800136a:	685b      	ldr	r3, [r3, #4]
 800136c:	2b02      	cmp	r3, #2
 800136e:	d107      	bne.n	8001380 <HAL_RCC_ClockConfig+0x88>
    {
      /* Check the HSE ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 8001370:	4b70      	ldr	r3, [pc, #448]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 8001372:	681a      	ldr	r2, [r3, #0]
 8001374:	2380      	movs	r3, #128	; 0x80
 8001376:	029b      	lsls	r3, r3, #10
 8001378:	4013      	ands	r3, r2
 800137a:	d120      	bne.n	80013be <HAL_RCC_ClockConfig+0xc6>
      {
        return HAL_ERROR;
 800137c:	2301      	movs	r3, #1
 800137e:	e0d3      	b.n	8001528 <HAL_RCC_ClockConfig+0x230>
      }
    }
    /* PLL is selected as System Clock Source */
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8001380:	687b      	ldr	r3, [r7, #4]
 8001382:	685b      	ldr	r3, [r3, #4]
 8001384:	2b03      	cmp	r3, #3
 8001386:	d107      	bne.n	8001398 <HAL_RCC_ClockConfig+0xa0>
    {
      /* Check the PLL ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 8001388:	4b6a      	ldr	r3, [pc, #424]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 800138a:	681a      	ldr	r2, [r3, #0]
 800138c:	2380      	movs	r3, #128	; 0x80
 800138e:	049b      	lsls	r3, r3, #18
 8001390:	4013      	ands	r3, r2
 8001392:	d114      	bne.n	80013be <HAL_RCC_ClockConfig+0xc6>
      {
        return HAL_ERROR;
 8001394:	2301      	movs	r3, #1
 8001396:	e0c7      	b.n	8001528 <HAL_RCC_ClockConfig+0x230>
      }
    }
    /* HSI is selected as System Clock Source */
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
 8001398:	687b      	ldr	r3, [r7, #4]
 800139a:	685b      	ldr	r3, [r3, #4]
 800139c:	2b01      	cmp	r3, #1
 800139e:	d106      	bne.n	80013ae <HAL_RCC_ClockConfig+0xb6>
    {
      /* Check the HSI ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 80013a0:	4b64      	ldr	r3, [pc, #400]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 80013a2:	681b      	ldr	r3, [r3, #0]
 80013a4:	2204      	movs	r2, #4
 80013a6:	4013      	ands	r3, r2
 80013a8:	d109      	bne.n	80013be <HAL_RCC_ClockConfig+0xc6>
      {
        return HAL_ERROR;
 80013aa:	2301      	movs	r3, #1
 80013ac:	e0bc      	b.n	8001528 <HAL_RCC_ClockConfig+0x230>
    }
    /* MSI is selected as System Clock Source */
    else
    {
      /* Check the MSI ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
 80013ae:	4b61      	ldr	r3, [pc, #388]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 80013b0:	681a      	ldr	r2, [r3, #0]
 80013b2:	2380      	movs	r3, #128	; 0x80
 80013b4:	009b      	lsls	r3, r3, #2
 80013b6:	4013      	ands	r3, r2
 80013b8:	d101      	bne.n	80013be <HAL_RCC_ClockConfig+0xc6>
      {
        return HAL_ERROR;
 80013ba:	2301      	movs	r3, #1
 80013bc:	e0b4      	b.n	8001528 <HAL_RCC_ClockConfig+0x230>
      }
    }
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 80013be:	4b5d      	ldr	r3, [pc, #372]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 80013c0:	68db      	ldr	r3, [r3, #12]
 80013c2:	2203      	movs	r2, #3
 80013c4:	4393      	bics	r3, r2
 80013c6:	0019      	movs	r1, r3
 80013c8:	687b      	ldr	r3, [r7, #4]
 80013ca:	685a      	ldr	r2, [r3, #4]
 80013cc:	4b59      	ldr	r3, [pc, #356]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 80013ce:	430a      	orrs	r2, r1
 80013d0:	60da      	str	r2, [r3, #12]

    /* Get Start Tick */
    tickstart = HAL_GetTick();
 80013d2:	f7ff f921 	bl	8000618 <HAL_GetTick>
 80013d6:	0003      	movs	r3, r0
 80013d8:	60fb      	str	r3, [r7, #12]

    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 80013da:	687b      	ldr	r3, [r7, #4]
 80013dc:	685b      	ldr	r3, [r3, #4]
 80013de:	2b02      	cmp	r3, #2
 80013e0:	d111      	bne.n	8001406 <HAL_RCC_ClockConfig+0x10e>
    {
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 80013e2:	e009      	b.n	80013f8 <HAL_RCC_ClockConfig+0x100>
      {
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 80013e4:	f7ff f918 	bl	8000618 <HAL_GetTick>
 80013e8:	0002      	movs	r2, r0
 80013ea:	68fb      	ldr	r3, [r7, #12]
 80013ec:	1ad3      	subs	r3, r2, r3
 80013ee:	4a52      	ldr	r2, [pc, #328]	; (8001538 <HAL_RCC_ClockConfig+0x240>)
 80013f0:	4293      	cmp	r3, r2
 80013f2:	d901      	bls.n	80013f8 <HAL_RCC_ClockConfig+0x100>
        {
          return HAL_TIMEOUT;
 80013f4:	2303      	movs	r3, #3
 80013f6:	e097      	b.n	8001528 <HAL_RCC_ClockConfig+0x230>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 80013f8:	4b4e      	ldr	r3, [pc, #312]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 80013fa:	68db      	ldr	r3, [r3, #12]
 80013fc:	220c      	movs	r2, #12
 80013fe:	4013      	ands	r3, r2
 8001400:	2b08      	cmp	r3, #8
 8001402:	d1ef      	bne.n	80013e4 <HAL_RCC_ClockConfig+0xec>
 8001404:	e03a      	b.n	800147c <HAL_RCC_ClockConfig+0x184>
        }
      }
    }
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8001406:	687b      	ldr	r3, [r7, #4]
 8001408:	685b      	ldr	r3, [r3, #4]
 800140a:	2b03      	cmp	r3, #3
 800140c:	d111      	bne.n	8001432 <HAL_RCC_ClockConfig+0x13a>
    {
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 800140e:	e009      	b.n	8001424 <HAL_RCC_ClockConfig+0x12c>
      {
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001410:	f7ff f902 	bl	8000618 <HAL_GetTick>
 8001414:	0002      	movs	r2, r0
 8001416:	68fb      	ldr	r3, [r7, #12]
 8001418:	1ad3      	subs	r3, r2, r3
 800141a:	4a47      	ldr	r2, [pc, #284]	; (8001538 <HAL_RCC_ClockConfig+0x240>)
 800141c:	4293      	cmp	r3, r2
 800141e:	d901      	bls.n	8001424 <HAL_RCC_ClockConfig+0x12c>
        {
          return HAL_TIMEOUT;
 8001420:	2303      	movs	r3, #3
 8001422:	e081      	b.n	8001528 <HAL_RCC_ClockConfig+0x230>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8001424:	4b43      	ldr	r3, [pc, #268]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 8001426:	68db      	ldr	r3, [r3, #12]
 8001428:	220c      	movs	r2, #12
 800142a:	4013      	ands	r3, r2
 800142c:	2b0c      	cmp	r3, #12
 800142e:	d1ef      	bne.n	8001410 <HAL_RCC_ClockConfig+0x118>
 8001430:	e024      	b.n	800147c <HAL_RCC_ClockConfig+0x184>
        }
      }
    }
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
 8001432:	687b      	ldr	r3, [r7, #4]
 8001434:	685b      	ldr	r3, [r3, #4]
 8001436:	2b01      	cmp	r3, #1
 8001438:	d11b      	bne.n	8001472 <HAL_RCC_ClockConfig+0x17a>
    {
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 800143a:	e009      	b.n	8001450 <HAL_RCC_ClockConfig+0x158>
      {
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 800143c:	f7ff f8ec 	bl	8000618 <HAL_GetTick>
 8001440:	0002      	movs	r2, r0
 8001442:	68fb      	ldr	r3, [r7, #12]
 8001444:	1ad3      	subs	r3, r2, r3
 8001446:	4a3c      	ldr	r2, [pc, #240]	; (8001538 <HAL_RCC_ClockConfig+0x240>)
 8001448:	4293      	cmp	r3, r2
 800144a:	d901      	bls.n	8001450 <HAL_RCC_ClockConfig+0x158>
        {
          return HAL_TIMEOUT;
 800144c:	2303      	movs	r3, #3
 800144e:	e06b      	b.n	8001528 <HAL_RCC_ClockConfig+0x230>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 8001450:	4b38      	ldr	r3, [pc, #224]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 8001452:	68db      	ldr	r3, [r3, #12]
 8001454:	220c      	movs	r2, #12
 8001456:	4013      	ands	r3, r2
 8001458:	2b04      	cmp	r3, #4
 800145a:	d1ef      	bne.n	800143c <HAL_RCC_ClockConfig+0x144>
 800145c:	e00e      	b.n	800147c <HAL_RCC_ClockConfig+0x184>
    }
    else
    {
      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
      {
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 800145e:	f7ff f8db 	bl	8000618 <HAL_GetTick>
 8001462:	0002      	movs	r2, r0
 8001464:	68fb      	ldr	r3, [r7, #12]
 8001466:	1ad3      	subs	r3, r2, r3
 8001468:	4a33      	ldr	r2, [pc, #204]	; (8001538 <HAL_RCC_ClockConfig+0x240>)
 800146a:	4293      	cmp	r3, r2
 800146c:	d901      	bls.n	8001472 <HAL_RCC_ClockConfig+0x17a>
        {
          return HAL_TIMEOUT;
 800146e:	2303      	movs	r3, #3
 8001470:	e05a      	b.n	8001528 <HAL_RCC_ClockConfig+0x230>
      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
 8001472:	4b30      	ldr	r3, [pc, #192]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 8001474:	68db      	ldr	r3, [r3, #12]
 8001476:	220c      	movs	r2, #12
 8001478:	4013      	ands	r3, r2
 800147a:	d1f0      	bne.n	800145e <HAL_RCC_ClockConfig+0x166>
        }
      }
    }
  }
  /* Decreasing the number of wait states because of lower CPU frequency */
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 800147c:	4b2c      	ldr	r3, [pc, #176]	; (8001530 <HAL_RCC_ClockConfig+0x238>)
 800147e:	681b      	ldr	r3, [r3, #0]
 8001480:	2201      	movs	r2, #1
 8001482:	4013      	ands	r3, r2
 8001484:	683a      	ldr	r2, [r7, #0]
 8001486:	429a      	cmp	r2, r3
 8001488:	d211      	bcs.n	80014ae <HAL_RCC_ClockConfig+0x1b6>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 800148a:	4b29      	ldr	r3, [pc, #164]	; (8001530 <HAL_RCC_ClockConfig+0x238>)
 800148c:	681b      	ldr	r3, [r3, #0]
 800148e:	2201      	movs	r2, #1
 8001490:	4393      	bics	r3, r2
 8001492:	0019      	movs	r1, r3
 8001494:	4b26      	ldr	r3, [pc, #152]	; (8001530 <HAL_RCC_ClockConfig+0x238>)
 8001496:	683a      	ldr	r2, [r7, #0]
 8001498:	430a      	orrs	r2, r1
 800149a:	601a      	str	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 800149c:	4b24      	ldr	r3, [pc, #144]	; (8001530 <HAL_RCC_ClockConfig+0x238>)
 800149e:	681b      	ldr	r3, [r3, #0]
 80014a0:	2201      	movs	r2, #1
 80014a2:	4013      	ands	r3, r2
 80014a4:	683a      	ldr	r2, [r7, #0]
 80014a6:	429a      	cmp	r2, r3
 80014a8:	d001      	beq.n	80014ae <HAL_RCC_ClockConfig+0x1b6>
    {
      return HAL_ERROR;
 80014aa:	2301      	movs	r3, #1
 80014ac:	e03c      	b.n	8001528 <HAL_RCC_ClockConfig+0x230>
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 80014ae:	687b      	ldr	r3, [r7, #4]
 80014b0:	681b      	ldr	r3, [r3, #0]
 80014b2:	2204      	movs	r2, #4
 80014b4:	4013      	ands	r3, r2
 80014b6:	d009      	beq.n	80014cc <HAL_RCC_ClockConfig+0x1d4>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 80014b8:	4b1e      	ldr	r3, [pc, #120]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 80014ba:	68db      	ldr	r3, [r3, #12]
 80014bc:	4a1f      	ldr	r2, [pc, #124]	; (800153c <HAL_RCC_ClockConfig+0x244>)
 80014be:	4013      	ands	r3, r2
 80014c0:	0019      	movs	r1, r3
 80014c2:	687b      	ldr	r3, [r7, #4]
 80014c4:	68da      	ldr	r2, [r3, #12]
 80014c6:	4b1b      	ldr	r3, [pc, #108]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 80014c8:	430a      	orrs	r2, r1
 80014ca:	60da      	str	r2, [r3, #12]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 80014cc:	687b      	ldr	r3, [r7, #4]
 80014ce:	681b      	ldr	r3, [r3, #0]
 80014d0:	2208      	movs	r2, #8
 80014d2:	4013      	ands	r3, r2
 80014d4:	d00a      	beq.n	80014ec <HAL_RCC_ClockConfig+0x1f4>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 80014d6:	4b17      	ldr	r3, [pc, #92]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 80014d8:	68db      	ldr	r3, [r3, #12]
 80014da:	4a19      	ldr	r2, [pc, #100]	; (8001540 <HAL_RCC_ClockConfig+0x248>)
 80014dc:	4013      	ands	r3, r2
 80014de:	0019      	movs	r1, r3
 80014e0:	687b      	ldr	r3, [r7, #4]
 80014e2:	691b      	ldr	r3, [r3, #16]
 80014e4:	00da      	lsls	r2, r3, #3
 80014e6:	4b13      	ldr	r3, [pc, #76]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 80014e8:	430a      	orrs	r2, r1
 80014ea:	60da      	str	r2, [r3, #12]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 80014ec:	f000 f82e 	bl	800154c <HAL_RCC_GetSysClockFreq>
 80014f0:	0001      	movs	r1, r0
 80014f2:	4b10      	ldr	r3, [pc, #64]	; (8001534 <HAL_RCC_ClockConfig+0x23c>)
 80014f4:	68db      	ldr	r3, [r3, #12]
 80014f6:	091b      	lsrs	r3, r3, #4
 80014f8:	220f      	movs	r2, #15
 80014fa:	4013      	ands	r3, r2
 80014fc:	4a11      	ldr	r2, [pc, #68]	; (8001544 <HAL_RCC_ClockConfig+0x24c>)
 80014fe:	5cd3      	ldrb	r3, [r2, r3]
 8001500:	000a      	movs	r2, r1
 8001502:	40da      	lsrs	r2, r3
 8001504:	4b10      	ldr	r3, [pc, #64]	; (8001548 <HAL_RCC_ClockConfig+0x250>)
 8001506:	601a      	str	r2, [r3, #0]

  /* Configure the source of time base considering new system clocks settings*/
  status = HAL_InitTick(TICK_INT_PRIORITY);
 8001508:	250b      	movs	r5, #11
 800150a:	197c      	adds	r4, r7, r5
 800150c:	2000      	movs	r0, #0
 800150e:	f7ff f83d 	bl	800058c <HAL_InitTick>
 8001512:	0003      	movs	r3, r0
 8001514:	7023      	strb	r3, [r4, #0]
  if(status != HAL_OK)
 8001516:	197b      	adds	r3, r7, r5
 8001518:	781b      	ldrb	r3, [r3, #0]
 800151a:	2b00      	cmp	r3, #0
 800151c:	d003      	beq.n	8001526 <HAL_RCC_ClockConfig+0x22e>
  {
    return status;
 800151e:	230b      	movs	r3, #11
 8001520:	18fb      	adds	r3, r7, r3
 8001522:	781b      	ldrb	r3, [r3, #0]
 8001524:	e000      	b.n	8001528 <HAL_RCC_ClockConfig+0x230>
  }

  return HAL_OK;
 8001526:	2300      	movs	r3, #0
}
 8001528:	0018      	movs	r0, r3
 800152a:	46bd      	mov	sp, r7
 800152c:	b004      	add	sp, #16
 800152e:	bdb0      	pop	{r4, r5, r7, pc}
 8001530:	40022000 	.word	0x40022000
 8001534:	40021000 	.word	0x40021000
 8001538:	00001388 	.word	0x00001388
 800153c:	fffff8ff 	.word	0xfffff8ff
 8001540:	ffffc7ff 	.word	0xffffc7ff
 8001544:	080019ac 	.word	0x080019ac
 8001548:	20000000 	.word	0x20000000

0800154c <HAL_RCC_GetSysClockFreq>:
  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 800154c:	b580      	push	{r7, lr}
 800154e:	b086      	sub	sp, #24
 8001550:	af00      	add	r7, sp, #0
  uint32_t tmpreg, pllm, plld, pllvco, msiclkrange;    /* no init needed */
  uint32_t sysclockfreq;

  tmpreg = RCC->CFGR;
 8001552:	4b3b      	ldr	r3, [pc, #236]	; (8001640 <HAL_RCC_GetSysClockFreq+0xf4>)
 8001554:	68db      	ldr	r3, [r3, #12]
 8001556:	60fb      	str	r3, [r7, #12]

  /* Get SYSCLK source -------------------------------------------------------*/
  switch (tmpreg & RCC_CFGR_SWS)
 8001558:	68fb      	ldr	r3, [r7, #12]
 800155a:	220c      	movs	r2, #12
 800155c:	4013      	ands	r3, r2
 800155e:	2b08      	cmp	r3, #8
 8001560:	d00e      	beq.n	8001580 <HAL_RCC_GetSysClockFreq+0x34>
 8001562:	2b0c      	cmp	r3, #12
 8001564:	d00f      	beq.n	8001586 <HAL_RCC_GetSysClockFreq+0x3a>
 8001566:	2b04      	cmp	r3, #4
 8001568:	d157      	bne.n	800161a <HAL_RCC_GetSysClockFreq+0xce>
  {
    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
    {
      if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
 800156a:	4b35      	ldr	r3, [pc, #212]	; (8001640 <HAL_RCC_GetSysClockFreq+0xf4>)
 800156c:	681b      	ldr	r3, [r3, #0]
 800156e:	2210      	movs	r2, #16
 8001570:	4013      	ands	r3, r2
 8001572:	d002      	beq.n	800157a <HAL_RCC_GetSysClockFreq+0x2e>
      {
        sysclockfreq =  (HSI_VALUE >> 2);
 8001574:	4b33      	ldr	r3, [pc, #204]	; (8001644 <HAL_RCC_GetSysClockFreq+0xf8>)
 8001576:	613b      	str	r3, [r7, #16]
      }
      else
      {
        sysclockfreq =  HSI_VALUE;
      }
      break;
 8001578:	e05d      	b.n	8001636 <HAL_RCC_GetSysClockFreq+0xea>
        sysclockfreq =  HSI_VALUE;
 800157a:	4b33      	ldr	r3, [pc, #204]	; (8001648 <HAL_RCC_GetSysClockFreq+0xfc>)
 800157c:	613b      	str	r3, [r7, #16]
      break;
 800157e:	e05a      	b.n	8001636 <HAL_RCC_GetSysClockFreq+0xea>
    }
    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
    {
      sysclockfreq = HSE_VALUE;
 8001580:	4b32      	ldr	r3, [pc, #200]	; (800164c <HAL_RCC_GetSysClockFreq+0x100>)
 8001582:	613b      	str	r3, [r7, #16]
      break;
 8001584:	e057      	b.n	8001636 <HAL_RCC_GetSysClockFreq+0xea>
    }
    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
    {
      pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
 8001586:	68fb      	ldr	r3, [r7, #12]
 8001588:	0c9b      	lsrs	r3, r3, #18
 800158a:	220f      	movs	r2, #15
 800158c:	4013      	ands	r3, r2
 800158e:	4a30      	ldr	r2, [pc, #192]	; (8001650 <HAL_RCC_GetSysClockFreq+0x104>)
 8001590:	5cd3      	ldrb	r3, [r2, r3]
 8001592:	60bb      	str	r3, [r7, #8]
      plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
 8001594:	68fb      	ldr	r3, [r7, #12]
 8001596:	0d9b      	lsrs	r3, r3, #22
 8001598:	2203      	movs	r2, #3
 800159a:	4013      	ands	r3, r2
 800159c:	3301      	adds	r3, #1
 800159e:	607b      	str	r3, [r7, #4]
      if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
 80015a0:	4b27      	ldr	r3, [pc, #156]	; (8001640 <HAL_RCC_GetSysClockFreq+0xf4>)
 80015a2:	68da      	ldr	r2, [r3, #12]
 80015a4:	2380      	movs	r3, #128	; 0x80
 80015a6:	025b      	lsls	r3, r3, #9
 80015a8:	4013      	ands	r3, r2
 80015aa:	d00f      	beq.n	80015cc <HAL_RCC_GetSysClockFreq+0x80>
      {
        /* HSE used as PLL clock source */
        pllvco = (HSE_VALUE * pllm) / plld;
 80015ac:	68b9      	ldr	r1, [r7, #8]
 80015ae:	000a      	movs	r2, r1
 80015b0:	0152      	lsls	r2, r2, #5
 80015b2:	1a52      	subs	r2, r2, r1
 80015b4:	0193      	lsls	r3, r2, #6
 80015b6:	1a9b      	subs	r3, r3, r2
 80015b8:	00db      	lsls	r3, r3, #3
 80015ba:	185b      	adds	r3, r3, r1
 80015bc:	025b      	lsls	r3, r3, #9
 80015be:	6879      	ldr	r1, [r7, #4]
 80015c0:	0018      	movs	r0, r3
 80015c2:	f7fe fda1 	bl	8000108 <__udivsi3>
 80015c6:	0003      	movs	r3, r0
 80015c8:	617b      	str	r3, [r7, #20]
 80015ca:	e023      	b.n	8001614 <HAL_RCC_GetSysClockFreq+0xc8>
      }
      else
      {
        if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
 80015cc:	4b1c      	ldr	r3, [pc, #112]	; (8001640 <HAL_RCC_GetSysClockFreq+0xf4>)
 80015ce:	681b      	ldr	r3, [r3, #0]
 80015d0:	2210      	movs	r2, #16
 80015d2:	4013      	ands	r3, r2
 80015d4:	d00f      	beq.n	80015f6 <HAL_RCC_GetSysClockFreq+0xaa>
        {
          pllvco = ((HSI_VALUE >> 2) * pllm) / plld;
 80015d6:	68b9      	ldr	r1, [r7, #8]
 80015d8:	000a      	movs	r2, r1
 80015da:	0152      	lsls	r2, r2, #5
 80015dc:	1a52      	subs	r2, r2, r1
 80015de:	0193      	lsls	r3, r2, #6
 80015e0:	1a9b      	subs	r3, r3, r2
 80015e2:	00db      	lsls	r3, r3, #3
 80015e4:	185b      	adds	r3, r3, r1
 80015e6:	021b      	lsls	r3, r3, #8
 80015e8:	6879      	ldr	r1, [r7, #4]
 80015ea:	0018      	movs	r0, r3
 80015ec:	f7fe fd8c 	bl	8000108 <__udivsi3>
 80015f0:	0003      	movs	r3, r0
 80015f2:	617b      	str	r3, [r7, #20]
 80015f4:	e00e      	b.n	8001614 <HAL_RCC_GetSysClockFreq+0xc8>
        }
        else
        {
         pllvco = (HSI_VALUE * pllm) / plld;
 80015f6:	68b9      	ldr	r1, [r7, #8]
 80015f8:	000a      	movs	r2, r1
 80015fa:	0152      	lsls	r2, r2, #5
 80015fc:	1a52      	subs	r2, r2, r1
 80015fe:	0193      	lsls	r3, r2, #6
 8001600:	1a9b      	subs	r3, r3, r2
 8001602:	00db      	lsls	r3, r3, #3
 8001604:	185b      	adds	r3, r3, r1
 8001606:	029b      	lsls	r3, r3, #10
 8001608:	6879      	ldr	r1, [r7, #4]
 800160a:	0018      	movs	r0, r3
 800160c:	f7fe fd7c 	bl	8000108 <__udivsi3>
 8001610:	0003      	movs	r3, r0
 8001612:	617b      	str	r3, [r7, #20]
        }
      }
      sysclockfreq = pllvco;
 8001614:	697b      	ldr	r3, [r7, #20]
 8001616:	613b      	str	r3, [r7, #16]
      break;
 8001618:	e00d      	b.n	8001636 <HAL_RCC_GetSysClockFreq+0xea>
    }
    case RCC_SYSCLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
    default: /* MSI used as system clock */
    {
      msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
 800161a:	4b09      	ldr	r3, [pc, #36]	; (8001640 <HAL_RCC_GetSysClockFreq+0xf4>)
 800161c:	685b      	ldr	r3, [r3, #4]
 800161e:	0b5b      	lsrs	r3, r3, #13
 8001620:	2207      	movs	r2, #7
 8001622:	4013      	ands	r3, r2
 8001624:	603b      	str	r3, [r7, #0]
      sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
 8001626:	683b      	ldr	r3, [r7, #0]
 8001628:	3301      	adds	r3, #1
 800162a:	2280      	movs	r2, #128	; 0x80
 800162c:	0212      	lsls	r2, r2, #8
 800162e:	409a      	lsls	r2, r3
 8001630:	0013      	movs	r3, r2
 8001632:	613b      	str	r3, [r7, #16]
      break;
 8001634:	46c0      	nop			; (mov r8, r8)
    }
  }
  return sysclockfreq;
 8001636:	693b      	ldr	r3, [r7, #16]
}
 8001638:	0018      	movs	r0, r3
 800163a:	46bd      	mov	sp, r7
 800163c:	b006      	add	sp, #24
 800163e:	bd80      	pop	{r7, pc}
 8001640:	40021000 	.word	0x40021000
 8001644:	003d0900 	.word	0x003d0900
 8001648:	00f42400 	.word	0x00f42400
 800164c:	007a1200 	.word	0x007a1200
 8001650:	080019bc 	.word	0x080019bc

08001654 <HAL_RCCEx_PeriphCLKConfig>:
  * @retval HAL status
  * @note   If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()
  *         to possibly update HSE divider.
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
 8001654:	b580      	push	{r7, lr}
 8001656:	b086      	sub	sp, #24
 8001658:	af00      	add	r7, sp, #0
 800165a:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

  /*------------------------------- RTC/LCD Configuration ------------------------*/
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
 800165c:	687b      	ldr	r3, [r7, #4]
 800165e:	681b      	ldr	r3, [r3, #0]
 8001660:	2220      	movs	r2, #32
 8001662:	4013      	ands	r3, r2
 8001664:	d106      	bne.n	8001674 <HAL_RCCEx_PeriphCLKConfig+0x20>
#if defined(LCD)
   || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
 8001666:	687b      	ldr	r3, [r7, #4]
 8001668:	681a      	ldr	r2, [r3, #0]
 800166a:	2380      	movs	r3, #128	; 0x80
 800166c:	011b      	lsls	r3, r3, #4
 800166e:	4013      	ands	r3, r2
 8001670:	d100      	bne.n	8001674 <HAL_RCCEx_PeriphCLKConfig+0x20>
 8001672:	e0dd      	b.n	8001830 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
    {
      assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection));
    }
#endif /* LCD */

    FlagStatus       pwrclkchanged = RESET;
 8001674:	2317      	movs	r3, #23
 8001676:	18fb      	adds	r3, r7, r3
 8001678:	2200      	movs	r2, #0
 800167a:	701a      	strb	r2, [r3, #0]

    /* As soon as function is called to change RTC clock source, activation of the
       power domain is done. */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 800167c:	4ba4      	ldr	r3, [pc, #656]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 800167e:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 8001680:	2380      	movs	r3, #128	; 0x80
 8001682:	055b      	lsls	r3, r3, #21
 8001684:	4013      	ands	r3, r2
 8001686:	d10a      	bne.n	800169e <HAL_RCCEx_PeriphCLKConfig+0x4a>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8001688:	4ba1      	ldr	r3, [pc, #644]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 800168a:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 800168c:	4ba0      	ldr	r3, [pc, #640]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 800168e:	2180      	movs	r1, #128	; 0x80
 8001690:	0549      	lsls	r1, r1, #21
 8001692:	430a      	orrs	r2, r1
 8001694:	639a      	str	r2, [r3, #56]	; 0x38
      pwrclkchanged = SET;
 8001696:	2317      	movs	r3, #23
 8001698:	18fb      	adds	r3, r7, r3
 800169a:	2201      	movs	r2, #1
 800169c:	701a      	strb	r2, [r3, #0]
    }

    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 800169e:	4b9d      	ldr	r3, [pc, #628]	; (8001914 <HAL_RCCEx_PeriphCLKConfig+0x2c0>)
 80016a0:	681a      	ldr	r2, [r3, #0]
 80016a2:	2380      	movs	r3, #128	; 0x80
 80016a4:	005b      	lsls	r3, r3, #1
 80016a6:	4013      	ands	r3, r2
 80016a8:	d11a      	bne.n	80016e0 <HAL_RCCEx_PeriphCLKConfig+0x8c>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 80016aa:	4b9a      	ldr	r3, [pc, #616]	; (8001914 <HAL_RCCEx_PeriphCLKConfig+0x2c0>)
 80016ac:	681a      	ldr	r2, [r3, #0]
 80016ae:	4b99      	ldr	r3, [pc, #612]	; (8001914 <HAL_RCCEx_PeriphCLKConfig+0x2c0>)
 80016b0:	2180      	movs	r1, #128	; 0x80
 80016b2:	0049      	lsls	r1, r1, #1
 80016b4:	430a      	orrs	r2, r1
 80016b6:	601a      	str	r2, [r3, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 80016b8:	f7fe ffae 	bl	8000618 <HAL_GetTick>
 80016bc:	0003      	movs	r3, r0
 80016be:	613b      	str	r3, [r7, #16]

      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80016c0:	e008      	b.n	80016d4 <HAL_RCCEx_PeriphCLKConfig+0x80>
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 80016c2:	f7fe ffa9 	bl	8000618 <HAL_GetTick>
 80016c6:	0002      	movs	r2, r0
 80016c8:	693b      	ldr	r3, [r7, #16]
 80016ca:	1ad3      	subs	r3, r2, r3
 80016cc:	2b64      	cmp	r3, #100	; 0x64
 80016ce:	d901      	bls.n	80016d4 <HAL_RCCEx_PeriphCLKConfig+0x80>
        {
          return HAL_TIMEOUT;
 80016d0:	2303      	movs	r3, #3
 80016d2:	e118      	b.n	8001906 <HAL_RCCEx_PeriphCLKConfig+0x2b2>
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80016d4:	4b8f      	ldr	r3, [pc, #572]	; (8001914 <HAL_RCCEx_PeriphCLKConfig+0x2c0>)
 80016d6:	681a      	ldr	r2, [r3, #0]
 80016d8:	2380      	movs	r3, #128	; 0x80
 80016da:	005b      	lsls	r3, r3, #1
 80016dc:	4013      	ands	r3, r2
 80016de:	d0f0      	beq.n	80016c2 <HAL_RCCEx_PeriphCLKConfig+0x6e>
        }
      }
    }

    /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
    temp_reg = (RCC->CR & RCC_CR_RTCPRE);
 80016e0:	4b8b      	ldr	r3, [pc, #556]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 80016e2:	681a      	ldr	r2, [r3, #0]
 80016e4:	23c0      	movs	r3, #192	; 0xc0
 80016e6:	039b      	lsls	r3, r3, #14
 80016e8:	4013      	ands	r3, r2
 80016ea:	60fb      	str	r3, [r7, #12]
    if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
 80016ec:	687b      	ldr	r3, [r7, #4]
 80016ee:	685a      	ldr	r2, [r3, #4]
 80016f0:	23c0      	movs	r3, #192	; 0xc0
 80016f2:	039b      	lsls	r3, r3, #14
 80016f4:	4013      	ands	r3, r2
 80016f6:	68fa      	ldr	r2, [r7, #12]
 80016f8:	429a      	cmp	r2, r3
 80016fa:	d107      	bne.n	800170c <HAL_RCCEx_PeriphCLKConfig+0xb8>
#if defined (LCD)
     || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
 80016fc:	687b      	ldr	r3, [r7, #4]
 80016fe:	689a      	ldr	r2, [r3, #8]
 8001700:	23c0      	movs	r3, #192	; 0xc0
 8001702:	039b      	lsls	r3, r3, #14
 8001704:	4013      	ands	r3, r2
 8001706:	68fa      	ldr	r2, [r7, #12]
 8001708:	429a      	cmp	r2, r3
 800170a:	d013      	beq.n	8001734 <HAL_RCCEx_PeriphCLKConfig+0xe0>
#endif /* LCD */
       )
    { /* Check HSE State */
      if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE)
 800170c:	687b      	ldr	r3, [r7, #4]
 800170e:	685a      	ldr	r2, [r3, #4]
 8001710:	23c0      	movs	r3, #192	; 0xc0
 8001712:	029b      	lsls	r3, r3, #10
 8001714:	401a      	ands	r2, r3
 8001716:	23c0      	movs	r3, #192	; 0xc0
 8001718:	029b      	lsls	r3, r3, #10
 800171a:	429a      	cmp	r2, r3
 800171c:	d10a      	bne.n	8001734 <HAL_RCCEx_PeriphCLKConfig+0xe0>
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
 800171e:	4b7c      	ldr	r3, [pc, #496]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001720:	681a      	ldr	r2, [r3, #0]
 8001722:	2380      	movs	r3, #128	; 0x80
 8001724:	029b      	lsls	r3, r3, #10
 8001726:	401a      	ands	r2, r3
 8001728:	2380      	movs	r3, #128	; 0x80
 800172a:	029b      	lsls	r3, r3, #10
 800172c:	429a      	cmp	r2, r3
 800172e:	d101      	bne.n	8001734 <HAL_RCCEx_PeriphCLKConfig+0xe0>
        {
          /* To update HSE divider, first switch-OFF HSE clock oscillator*/
          return HAL_ERROR;
 8001730:	2301      	movs	r3, #1
 8001732:	e0e8      	b.n	8001906 <HAL_RCCEx_PeriphCLKConfig+0x2b2>
        }
      }
    }

    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
    temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);
 8001734:	4b76      	ldr	r3, [pc, #472]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001736:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 8001738:	23c0      	movs	r3, #192	; 0xc0
 800173a:	029b      	lsls	r3, r3, #10
 800173c:	4013      	ands	r3, r2
 800173e:	60fb      	str	r3, [r7, #12]

    if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \
 8001740:	68fb      	ldr	r3, [r7, #12]
 8001742:	2b00      	cmp	r3, #0
 8001744:	d049      	beq.n	80017da <HAL_RCCEx_PeriphCLKConfig+0x186>
 8001746:	687b      	ldr	r3, [r7, #4]
 8001748:	685a      	ldr	r2, [r3, #4]
 800174a:	23c0      	movs	r3, #192	; 0xc0
 800174c:	029b      	lsls	r3, r3, #10
 800174e:	4013      	ands	r3, r2
 8001750:	68fa      	ldr	r2, [r7, #12]
 8001752:	429a      	cmp	r2, r3
 8001754:	d004      	beq.n	8001760 <HAL_RCCEx_PeriphCLKConfig+0x10c>
      && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 8001756:	687b      	ldr	r3, [r7, #4]
 8001758:	681b      	ldr	r3, [r3, #0]
 800175a:	2220      	movs	r2, #32
 800175c:	4013      	ands	r3, r2
 800175e:	d10d      	bne.n	800177c <HAL_RCCEx_PeriphCLKConfig+0x128>
#if defined(LCD)
      || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \
 8001760:	687b      	ldr	r3, [r7, #4]
 8001762:	689a      	ldr	r2, [r3, #8]
 8001764:	23c0      	movs	r3, #192	; 0xc0
 8001766:	029b      	lsls	r3, r3, #10
 8001768:	4013      	ands	r3, r2
 800176a:	68fa      	ldr	r2, [r7, #12]
 800176c:	429a      	cmp	r2, r3
 800176e:	d034      	beq.n	80017da <HAL_RCCEx_PeriphCLKConfig+0x186>
       && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))
 8001770:	687b      	ldr	r3, [r7, #4]
 8001772:	681a      	ldr	r2, [r3, #0]
 8001774:	2380      	movs	r3, #128	; 0x80
 8001776:	011b      	lsls	r3, r3, #4
 8001778:	4013      	ands	r3, r2
 800177a:	d02e      	beq.n	80017da <HAL_RCCEx_PeriphCLKConfig+0x186>
#endif /* LCD */
     ))
    {
      /* Store the content of CSR register before the reset of Backup Domain */
      temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
 800177c:	4b64      	ldr	r3, [pc, #400]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 800177e:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 8001780:	4a65      	ldr	r2, [pc, #404]	; (8001918 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
 8001782:	4013      	ands	r3, r2
 8001784:	60fb      	str	r3, [r7, #12]

      /* RTC Clock selection can be changed only if the Backup Domain is reset */
      __HAL_RCC_BACKUPRESET_FORCE();
 8001786:	4b62      	ldr	r3, [pc, #392]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001788:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 800178a:	4b61      	ldr	r3, [pc, #388]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 800178c:	2180      	movs	r1, #128	; 0x80
 800178e:	0309      	lsls	r1, r1, #12
 8001790:	430a      	orrs	r2, r1
 8001792:	651a      	str	r2, [r3, #80]	; 0x50
      __HAL_RCC_BACKUPRESET_RELEASE();
 8001794:	4b5e      	ldr	r3, [pc, #376]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001796:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 8001798:	4b5d      	ldr	r3, [pc, #372]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 800179a:	4960      	ldr	r1, [pc, #384]	; (800191c <HAL_RCCEx_PeriphCLKConfig+0x2c8>)
 800179c:	400a      	ands	r2, r1
 800179e:	651a      	str	r2, [r3, #80]	; 0x50

      /* Restore the Content of CSR register */
      RCC->CSR = temp_reg;
 80017a0:	4b5b      	ldr	r3, [pc, #364]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 80017a2:	68fa      	ldr	r2, [r7, #12]
 80017a4:	651a      	str	r2, [r3, #80]	; 0x50

       /* Wait for LSERDY if LSE was enabled */
      if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
 80017a6:	68fa      	ldr	r2, [r7, #12]
 80017a8:	2380      	movs	r3, #128	; 0x80
 80017aa:	005b      	lsls	r3, r3, #1
 80017ac:	4013      	ands	r3, r2
 80017ae:	d014      	beq.n	80017da <HAL_RCCEx_PeriphCLKConfig+0x186>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80017b0:	f7fe ff32 	bl	8000618 <HAL_GetTick>
 80017b4:	0003      	movs	r3, r0
 80017b6:	613b      	str	r3, [r7, #16]

        /* Wait till LSE is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 80017b8:	e009      	b.n	80017ce <HAL_RCCEx_PeriphCLKConfig+0x17a>
        {
          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 80017ba:	f7fe ff2d 	bl	8000618 <HAL_GetTick>
 80017be:	0002      	movs	r2, r0
 80017c0:	693b      	ldr	r3, [r7, #16]
 80017c2:	1ad3      	subs	r3, r2, r3
 80017c4:	4a56      	ldr	r2, [pc, #344]	; (8001920 <HAL_RCCEx_PeriphCLKConfig+0x2cc>)
 80017c6:	4293      	cmp	r3, r2
 80017c8:	d901      	bls.n	80017ce <HAL_RCCEx_PeriphCLKConfig+0x17a>
          {
            return HAL_TIMEOUT;
 80017ca:	2303      	movs	r3, #3
 80017cc:	e09b      	b.n	8001906 <HAL_RCCEx_PeriphCLKConfig+0x2b2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 80017ce:	4b50      	ldr	r3, [pc, #320]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 80017d0:	6d1a      	ldr	r2, [r3, #80]	; 0x50
 80017d2:	2380      	movs	r3, #128	; 0x80
 80017d4:	009b      	lsls	r3, r3, #2
 80017d6:	4013      	ands	r3, r2
 80017d8:	d0ef      	beq.n	80017ba <HAL_RCCEx_PeriphCLKConfig+0x166>
          }
        }
      }
    }
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 80017da:	687b      	ldr	r3, [r7, #4]
 80017dc:	685a      	ldr	r2, [r3, #4]
 80017de:	23c0      	movs	r3, #192	; 0xc0
 80017e0:	029b      	lsls	r3, r3, #10
 80017e2:	401a      	ands	r2, r3
 80017e4:	23c0      	movs	r3, #192	; 0xc0
 80017e6:	029b      	lsls	r3, r3, #10
 80017e8:	429a      	cmp	r2, r3
 80017ea:	d10c      	bne.n	8001806 <HAL_RCCEx_PeriphCLKConfig+0x1b2>
 80017ec:	4b48      	ldr	r3, [pc, #288]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 80017ee:	681b      	ldr	r3, [r3, #0]
 80017f0:	4a4c      	ldr	r2, [pc, #304]	; (8001924 <HAL_RCCEx_PeriphCLKConfig+0x2d0>)
 80017f2:	4013      	ands	r3, r2
 80017f4:	0019      	movs	r1, r3
 80017f6:	687b      	ldr	r3, [r7, #4]
 80017f8:	685a      	ldr	r2, [r3, #4]
 80017fa:	23c0      	movs	r3, #192	; 0xc0
 80017fc:	039b      	lsls	r3, r3, #14
 80017fe:	401a      	ands	r2, r3
 8001800:	4b43      	ldr	r3, [pc, #268]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001802:	430a      	orrs	r2, r1
 8001804:	601a      	str	r2, [r3, #0]
 8001806:	4b42      	ldr	r3, [pc, #264]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001808:	6d19      	ldr	r1, [r3, #80]	; 0x50
 800180a:	687b      	ldr	r3, [r7, #4]
 800180c:	685a      	ldr	r2, [r3, #4]
 800180e:	23c0      	movs	r3, #192	; 0xc0
 8001810:	029b      	lsls	r3, r3, #10
 8001812:	401a      	ands	r2, r3
 8001814:	4b3e      	ldr	r3, [pc, #248]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001816:	430a      	orrs	r2, r1
 8001818:	651a      	str	r2, [r3, #80]	; 0x50

    /* Require to disable power clock if necessary */
    if(pwrclkchanged == SET)
 800181a:	2317      	movs	r3, #23
 800181c:	18fb      	adds	r3, r7, r3
 800181e:	781b      	ldrb	r3, [r3, #0]
 8001820:	2b01      	cmp	r3, #1
 8001822:	d105      	bne.n	8001830 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8001824:	4b3a      	ldr	r3, [pc, #232]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001826:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 8001828:	4b39      	ldr	r3, [pc, #228]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 800182a:	493f      	ldr	r1, [pc, #252]	; (8001928 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
 800182c:	400a      	ands	r2, r1
 800182e:	639a      	str	r2, [r3, #56]	; 0x38
    }
  }

#if defined (RCC_CCIPR_USART1SEL)
  /*------------------------------- USART1 Configuration ------------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
 8001830:	687b      	ldr	r3, [r7, #4]
 8001832:	681b      	ldr	r3, [r3, #0]
 8001834:	2201      	movs	r2, #1
 8001836:	4013      	ands	r3, r2
 8001838:	d009      	beq.n	800184e <HAL_RCCEx_PeriphCLKConfig+0x1fa>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));

    /* Configure the USART1 clock source */
    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
 800183a:	4b35      	ldr	r3, [pc, #212]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 800183c:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 800183e:	2203      	movs	r2, #3
 8001840:	4393      	bics	r3, r2
 8001842:	0019      	movs	r1, r3
 8001844:	687b      	ldr	r3, [r7, #4]
 8001846:	68da      	ldr	r2, [r3, #12]
 8001848:	4b31      	ldr	r3, [pc, #196]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 800184a:	430a      	orrs	r2, r1
 800184c:	64da      	str	r2, [r3, #76]	; 0x4c
  }
#endif /* RCC_CCIPR_USART1SEL */

  /*----------------------------- USART2 Configuration --------------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
 800184e:	687b      	ldr	r3, [r7, #4]
 8001850:	681b      	ldr	r3, [r3, #0]
 8001852:	2202      	movs	r2, #2
 8001854:	4013      	ands	r3, r2
 8001856:	d009      	beq.n	800186c <HAL_RCCEx_PeriphCLKConfig+0x218>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));

    /* Configure the USART2 clock source */
    __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
 8001858:	4b2d      	ldr	r3, [pc, #180]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 800185a:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 800185c:	220c      	movs	r2, #12
 800185e:	4393      	bics	r3, r2
 8001860:	0019      	movs	r1, r3
 8001862:	687b      	ldr	r3, [r7, #4]
 8001864:	691a      	ldr	r2, [r3, #16]
 8001866:	4b2a      	ldr	r3, [pc, #168]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001868:	430a      	orrs	r2, r1
 800186a:	64da      	str	r2, [r3, #76]	; 0x4c
  }

  /*------------------------------ LPUART1 Configuration ------------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
 800186c:	687b      	ldr	r3, [r7, #4]
 800186e:	681b      	ldr	r3, [r3, #0]
 8001870:	2204      	movs	r2, #4
 8001872:	4013      	ands	r3, r2
 8001874:	d009      	beq.n	800188a <HAL_RCCEx_PeriphCLKConfig+0x236>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));

    /* Configure the LPUAR1 clock source */
    __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
 8001876:	4b26      	ldr	r3, [pc, #152]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001878:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 800187a:	4a2c      	ldr	r2, [pc, #176]	; (800192c <HAL_RCCEx_PeriphCLKConfig+0x2d8>)
 800187c:	4013      	ands	r3, r2
 800187e:	0019      	movs	r1, r3
 8001880:	687b      	ldr	r3, [r7, #4]
 8001882:	695a      	ldr	r2, [r3, #20]
 8001884:	4b22      	ldr	r3, [pc, #136]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001886:	430a      	orrs	r2, r1
 8001888:	64da      	str	r2, [r3, #76]	; 0x4c
  }

  /*------------------------------ I2C1 Configuration ------------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
 800188a:	687b      	ldr	r3, [r7, #4]
 800188c:	681b      	ldr	r3, [r3, #0]
 800188e:	2208      	movs	r2, #8
 8001890:	4013      	ands	r3, r2
 8001892:	d009      	beq.n	80018a8 <HAL_RCCEx_PeriphCLKConfig+0x254>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));

    /* Configure the I2C1 clock source */
    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
 8001894:	4b1e      	ldr	r3, [pc, #120]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001896:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8001898:	4a25      	ldr	r2, [pc, #148]	; (8001930 <HAL_RCCEx_PeriphCLKConfig+0x2dc>)
 800189a:	4013      	ands	r3, r2
 800189c:	0019      	movs	r1, r3
 800189e:	687b      	ldr	r3, [r7, #4]
 80018a0:	699a      	ldr	r2, [r3, #24]
 80018a2:	4b1b      	ldr	r3, [pc, #108]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 80018a4:	430a      	orrs	r2, r1
 80018a6:	64da      	str	r2, [r3, #76]	; 0x4c
  }

#if defined (RCC_CCIPR_I2C3SEL)
    /*------------------------------ I2C3 Configuration ------------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
 80018a8:	687b      	ldr	r3, [r7, #4]
 80018aa:	681a      	ldr	r2, [r3, #0]
 80018ac:	2380      	movs	r3, #128	; 0x80
 80018ae:	005b      	lsls	r3, r3, #1
 80018b0:	4013      	ands	r3, r2
 80018b2:	d009      	beq.n	80018c8 <HAL_RCCEx_PeriphCLKConfig+0x274>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));

    /* Configure the I2C3 clock source */
    __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
 80018b4:	4b16      	ldr	r3, [pc, #88]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 80018b6:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80018b8:	4a17      	ldr	r2, [pc, #92]	; (8001918 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
 80018ba:	4013      	ands	r3, r2
 80018bc:	0019      	movs	r1, r3
 80018be:	687b      	ldr	r3, [r7, #4]
 80018c0:	69da      	ldr	r2, [r3, #28]
 80018c2:	4b13      	ldr	r3, [pc, #76]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 80018c4:	430a      	orrs	r2, r1
 80018c6:	64da      	str	r2, [r3, #76]	; 0x4c
  }
#endif /* RCC_CCIPR_I2C3SEL */

#if defined(USB)
 /*---------------------------- USB and RNG configuration --------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
 80018c8:	687b      	ldr	r3, [r7, #4]
 80018ca:	681b      	ldr	r3, [r3, #0]
 80018cc:	2240      	movs	r2, #64	; 0x40
 80018ce:	4013      	ands	r3, r2
 80018d0:	d009      	beq.n	80018e6 <HAL_RCCEx_PeriphCLKConfig+0x292>
  {
    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 80018d2:	4b0f      	ldr	r3, [pc, #60]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 80018d4:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80018d6:	4a17      	ldr	r2, [pc, #92]	; (8001934 <HAL_RCCEx_PeriphCLKConfig+0x2e0>)
 80018d8:	4013      	ands	r3, r2
 80018da:	0019      	movs	r1, r3
 80018dc:	687b      	ldr	r3, [r7, #4]
 80018de:	6a5a      	ldr	r2, [r3, #36]	; 0x24
 80018e0:	4b0b      	ldr	r3, [pc, #44]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 80018e2:	430a      	orrs	r2, r1
 80018e4:	64da      	str	r2, [r3, #76]	; 0x4c
  }
#endif /* USB */

  /*---------------------------- LPTIM1 configuration ------------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
 80018e6:	687b      	ldr	r3, [r7, #4]
 80018e8:	681b      	ldr	r3, [r3, #0]
 80018ea:	2280      	movs	r2, #128	; 0x80
 80018ec:	4013      	ands	r3, r2
 80018ee:	d009      	beq.n	8001904 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
  {
    assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection));
    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection);
 80018f0:	4b07      	ldr	r3, [pc, #28]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 80018f2:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 80018f4:	4a10      	ldr	r2, [pc, #64]	; (8001938 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
 80018f6:	4013      	ands	r3, r2
 80018f8:	0019      	movs	r1, r3
 80018fa:	687b      	ldr	r3, [r7, #4]
 80018fc:	6a1a      	ldr	r2, [r3, #32]
 80018fe:	4b04      	ldr	r3, [pc, #16]	; (8001910 <HAL_RCCEx_PeriphCLKConfig+0x2bc>)
 8001900:	430a      	orrs	r2, r1
 8001902:	64da      	str	r2, [r3, #76]	; 0x4c
  }

  return HAL_OK;
 8001904:	2300      	movs	r3, #0
}
 8001906:	0018      	movs	r0, r3
 8001908:	46bd      	mov	sp, r7
 800190a:	b006      	add	sp, #24
 800190c:	bd80      	pop	{r7, pc}
 800190e:	46c0      	nop			; (mov r8, r8)
 8001910:	40021000 	.word	0x40021000
 8001914:	40007000 	.word	0x40007000
 8001918:	fffcffff 	.word	0xfffcffff
 800191c:	fff7ffff 	.word	0xfff7ffff
 8001920:	00001388 	.word	0x00001388
 8001924:	ffcfffff 	.word	0xffcfffff
 8001928:	efffffff 	.word	0xefffffff
 800192c:	fffff3ff 	.word	0xfffff3ff
 8001930:	ffffcfff 	.word	0xffffcfff
 8001934:	fbffffff 	.word	0xfbffffff
 8001938:	fff3ffff 	.word	0xfff3ffff

0800193c <__libc_init_array>:
 800193c:	b570      	push	{r4, r5, r6, lr}
 800193e:	2600      	movs	r6, #0
 8001940:	4d0c      	ldr	r5, [pc, #48]	; (8001974 <__libc_init_array+0x38>)
 8001942:	4c0d      	ldr	r4, [pc, #52]	; (8001978 <__libc_init_array+0x3c>)
 8001944:	1b64      	subs	r4, r4, r5
 8001946:	10a4      	asrs	r4, r4, #2
 8001948:	42a6      	cmp	r6, r4
 800194a:	d109      	bne.n	8001960 <__libc_init_array+0x24>
 800194c:	2600      	movs	r6, #0
 800194e:	f000 f821 	bl	8001994 <_init>
 8001952:	4d0a      	ldr	r5, [pc, #40]	; (800197c <__libc_init_array+0x40>)
 8001954:	4c0a      	ldr	r4, [pc, #40]	; (8001980 <__libc_init_array+0x44>)
 8001956:	1b64      	subs	r4, r4, r5
 8001958:	10a4      	asrs	r4, r4, #2
 800195a:	42a6      	cmp	r6, r4
 800195c:	d105      	bne.n	800196a <__libc_init_array+0x2e>
 800195e:	bd70      	pop	{r4, r5, r6, pc}
 8001960:	00b3      	lsls	r3, r6, #2
 8001962:	58eb      	ldr	r3, [r5, r3]
 8001964:	4798      	blx	r3
 8001966:	3601      	adds	r6, #1
 8001968:	e7ee      	b.n	8001948 <__libc_init_array+0xc>
 800196a:	00b3      	lsls	r3, r6, #2
 800196c:	58eb      	ldr	r3, [r5, r3]
 800196e:	4798      	blx	r3
 8001970:	3601      	adds	r6, #1
 8001972:	e7f2      	b.n	800195a <__libc_init_array+0x1e>
 8001974:	080019c8 	.word	0x080019c8
 8001978:	080019c8 	.word	0x080019c8
 800197c:	080019c8 	.word	0x080019c8
 8001980:	080019cc 	.word	0x080019cc

08001984 <memset>:
 8001984:	0003      	movs	r3, r0
 8001986:	1812      	adds	r2, r2, r0
 8001988:	4293      	cmp	r3, r2
 800198a:	d100      	bne.n	800198e <memset+0xa>
 800198c:	4770      	bx	lr
 800198e:	7019      	strb	r1, [r3, #0]
 8001990:	3301      	adds	r3, #1
 8001992:	e7f9      	b.n	8001988 <memset+0x4>

08001994 <_init>:
 8001994:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8001996:	46c0      	nop			; (mov r8, r8)
 8001998:	bcf8      	pop	{r3, r4, r5, r6, r7}
 800199a:	bc08      	pop	{r3}
 800199c:	469e      	mov	lr, r3
 800199e:	4770      	bx	lr

080019a0 <_fini>:
 80019a0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80019a2:	46c0      	nop			; (mov r8, r8)
 80019a4:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80019a6:	bc08      	pop	{r3}
 80019a8:	469e      	mov	lr, r3
 80019aa:	4770      	bx	lr
